![]() Production FED
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The FED-UK Pages17 July, 2008 |
Please look at the Master FED Project Documentation pages for further information Manuals, Firmware, Schematics etc
FED Final Production Delivery Summary
CERN USC55 ELOG VME Installation
RAL status report
RAL status report
RAL status report
RAL status report
RAL status report
RAL status report
RAL status report
RAL status report
RAL status report
RAL status report
FED register dumps
RAL status report
Low Level Software (Jo)
RAL status report
CERN report (Oz)
RAL status report
CERN report (Oz)
Software Plans slides (Jo Cole)
RAL status report
Firmware and Integration status slides (Oz)
RAL status report
Fake Frame slides (Oz)
Cluster Finding slides (James)
RAL INS status report
RAL INS status report
RAL INS status report ; Updated remaining firmware requirements
Software developments at CERN (Jon)
FEDTester TTC interface (on Greg's pages)
RAL INS status report ; Full Crate test schematic
FE FPGA Verilog to VHDL slides (Osman)
PPD system setup ; header format (Ian)
RAL INS status report ; proposed header formats 1a (Full debug) ; 2 ; 3 ; 4 (ZS min debug)
CALICE status (Ozman)
S-LINK test results (James)
RAL INS status report
RAL INS status report
RAL INS status report
RAL INS status report
Transition Card status (James)
Summary of FEDv1 (DDi) assembly faults.
Draft Document and Flow Chart 1, Flow Chart 2 on Testing at Assembly plant.
CERN DAQ Card Testing LabView Example Operator GUI.
Very draft Manufacturing Spec
RAL INS status report
RAL Temperature measurements with 5 FEDs results ; crate pictures
Boundary Scan slides (Ivan)
CERN report (Jonathan)
Test progress report (Matt N.)
RAL INS status report
RAL INS status report
S-LINK update (James)
Temperature measurements web pages (Greg)
Power requirements note_v2 (Costas)
RAL INS status report
Front-End FPGA Test Results (Matt P.)
Diamond crate cabling pictures (Matt P.)
S-LINK progress Results (James)
RAL INS status report
CERN software status report (Jon)
PPD Front-End FPGA Test Results (Gareth)
S-LINK data transfer Test Results (James)
S-LINK signals Test Results (Costas)
FED Testing at Assembly Company Draft Note (Matt N.)
RAL INS status report
Updated Power Measurements
RAL INS status report
RAL INS status report
RAL INS status report
Agenda
Agenda
RAL INS status report
RAL INS status report
FED Opto Tester status
FED Analogue tests status
RAL INS status report
RAL INS status report
PSPICE simulations (James)
FED Tester status report
RAL INS status report
Firmware Schedule for Q3/03
FED buffering note (Emlyn)
Agenda
RAL INS status report
Low-Level Software status (Matthew P.)
Agenda
RAL INS status report
RAL INS status report
FED Buffers Emlyn
Crates Costas
RAL INS status report
RAL INS status report
Slides describing proposed test schedule v1.4 (see Planning above)
FEDv1 RAL status report
RAL INS status report
FPGA Firmware Design presentation (Rob)
RAL INS status report
RAL INS status report
FED Tester Board status report (Matt Noy)
Agenda
RAL INS status report
RAL INS status report
FED-PMC status
Draft Reply to Piero Verdini's Module Tester document
RAL INS status report
FED Electrical Test Card (James Salisbury)
FED Tester Software (Matt Noy)
Minutes & Actions
RAL INS status report
Minutes & Actions
RAL INS status report
Minutes & Actions
FED crate requirements draft
RAL INS status report
Draft Test Plan for FF1
RAL INS status report
Rob's FED slides
Greg's APVE slides
Comments on VME64x and cPCI
FE Module Design James Salisbury
Minutes & Actions
Minutes & Actions
Opto-Tester card by Matt
Minutes&Actions
Status report by John.
Presentations by John (PMC, Final-FED status, Attila's Questions and DAQ Links) and Rob (Clock Distribution, Ancillary circuits).
Front-End Module layout (August 2001)
[Go to Final-FED Public page]