Osmonde Zorba is a new IC engineer who will be working on the FED related activity.
Analogue Front-End: James Salisbury has found it necessary to replace the single Op-Amp by two Op-Amps in series, in order to solve instability problems. These problems have put the analogue stage 4 weeks behind schedule, but it is not believed that this will delay the overall FED schedule. Adam Baird's request for a change in the Opto-Rx pin-outs is being considered by F.Vasey.
The question was raised as to whether we should produce a special board containing only the analogue stage, in order to verify that this parts works OK. However, given the current FED schedule, this doesn't seem reasonable.
Delay chip: Pin-out is done. Phase control still being studied.
VME interface: Not done. Will probably be deferred - with no effect on overall FED schedule.
Power: Saeed Taghavirad has evaluated the FED power requirements. The +1.5V and -5V must be derived on the FED board. Rob Halsall suspects that even the +3.3V might need to be, since although this is ~ a VME standard, the VME standard ramping speed for voltage turn-on might not suit our FPGAs.
Digital Back-End: To be completed by Rob Halsall and Saeed Taghavirad.
Opto-Rx: We are not sure if the 3W heat leaves the Opto-Rx through the top (via cooling fins) or through the bottom (via the VME board). In the latter case, the PCB design may need modifying. and also conducting glues may be reqired to attach the Opto-Rx to the PCB.
FMM modules will collect the Busy/Ready etc. signals from the FEDs and send them to the trigger contol system. The RUWG proposes that FED crates should no longer contain an FMM. Instead, all FMMs will be stored in TRIDAS racks, and each individual FED will send its fast signals to them there. As we don't want to send ~500 lots of fast signals to the FMMs, this reraises the question of whether we can wire-OR the outputs of all the FEDs in a rack, and just send one lot of fast signals to the FMM per FED rack. The disadvantage of this is that it is less flexible than the old scheme where one FMM was in each FED rack.
1) Test digital chip inter-connections with JTAG boundary scan.
2) Check that we can talk to the FED via VME.
3) Test analogue-front-end chip inter-connections by injecting analogue voltage into ADC,
and looking at the ADC output by installing a ChipScope logic analyser in the first
(delay) FPGA. Not yet clear how to inject electrical inputs into ADC. Either solder wire
onto the resistor (into which the Opto-Rx output normally goes), or better, use a
spring-loaded connection.
4) Check functioning of digital electronics by injecting signals into it using Delay FPGA,
and analysing resulting signals elsewhere in the FED using ChipScope in the FPGAs.
5) Inject electrical, emulated APV signals using IC FED-tester.
6) Attach Opto-Rx to the FED. Mark Raymond reckons we could do this ourselves, possibly
testing the FED, after adding each one.
7) Inject optical, emulated APV signals using IC FED-tester.
Version 1 of the FED tester may rely on a SEQSI to inject digital sequences into the DAC. It may also use the VME Electrical-Opto converters which have been used in beam-tests.
To reduce the number of Final FEDs required for module testing, Ariella Cattai is considering reading the output from the Tracker Rod/Petal opto-links into an opto-elec converter, followed by an electrical switch, which can switch several signals into one PMC-FED input. A meeting will be held at CERN to discuss this.
* RAL: Wed. 27th March at 14:30.
* K.Bell should write statement for DAQ group on how we want S-Link to connect to FED.
This is getting urgent.
* I.Tomalin to take minutes when K.Bell not around.
* C.Foudas to consider implications of new FMM scheme (see above).
* R.Halsall to ask F.Vasey whether Opto-Rx loses heat through top or bottom (see above).
* R.Halsall will consider organising a trip to a manufacturing company during the next few
months.
Minutes produced by Ian Tomalin.