| PR002
Jan-2003 (ST) |
Problem report generated by the Assembly company SAETECH.
There are a number of incorrect shapes used on the pcb. To be investigated by PCB design group and correct for CMS FED V2.
Footprints for D28,D29 and D33 have now been fixed. The footprints for the HBAT-540C / HBAT-5402 have been fixed. Schematics need changing from HBAT-540C to HBAT-5402
|
| PR003
28-01-2003 (ST) |
Complementary output of LM393M (U127 & U137) was
reversed.
This was corrected for U127 by cutting links and swapping the outputs, for U137 there are no links so the device was removed together with R372 and R373 to bypass the circuit. The schematics have to be updated to show these changes. To fix replace U127 and associated circuitry with a MAX6319LHUK46CT, this will improve reliability and save space. a MAX708 part is also being considered, as the MAX708will be used as a replacement for U137 Futher to above note it has been noted that both the 4000 series logic and the TPS3510 both require a logic high pulse. Both LK59 and LK60 should be connected to pin 7 of the comparator U127. Pin 1 should be disconnected.
|
| PR004
28-01-2003 (ST) |
C3402 was fitted even though it is marked as DO NOT FIT.
This was corrected by removing the capacitor. The assembly notes to be checked to ensure this component is marked as DO NOT FIT.
|
| PR005
28-01-2003 (ST) |
Timing period on U140 MAX5906 is marginal.
This caused the power to board to be intermittent. Was rectified by changing the value of resistors R394 and R1240 to 470K. James Salisbury to perform more tests to finalise the value of resistors for CMS FED V2.
|
| PR006
28-01-2003 (ST) |
Enable pin (1) on U135 TPS75725 is connected to 3.3V. This caused the linear regulator to be disabled. Was rectified by connecting the pin to ground. Modify circuit schematics for CMS FED V2. The symbol should be updated and the circle replaced with a negation bar
|
| PR007
28-01-2003 (ST) |
Power up sequence of power rails are incorrect. Wrong power up sequence caused the QDR memories to get very hot. James Salisbury to perform more tests to establish the correct powering sequence for CMS FED V2. (1.5V to come up after 2.5V) Modify circuit schematics for CMS FED V2.
|
| PR008
05-02-2003 (ST) |
LVDS termination resistors missing. Termination resistors on LVDS clock signals between Back End and VME FPGAs do not exist. Modify circuit schematics by adding 100R termination resistors on signals CLK_LVDS_VME & CLK_LVDS_TTC for CMS FED V2.
|
| PR009
05-02-2003 (ST) |
Under voltage trip on 3.3V rail causes the power to the card
to shut down and start up again. The under voltage of the 3.3V rail causes the power to board to shut down and restart over and over. James Salisbury to investigate this fault condition. This was in part due to the high impedance of the power cables, power supplies must be connected to the back planes by short thick buss bars. At 13A, 23 mOhms will loose 10% of 3.3V Modify circuit schematics for CMS FED V2.
|
| PR010
12-02-2003 (ST) |
PGOOD+5V susceptible to noise on monitor input of U140.
Capacitor (1nF) added to filter out high frequency noise on the monitor input of U140. See note for PR009 Modify circuit schematics for CMS FED V2.
|
| PR011
27-03-2003 (JS) |
The precidip connector used
on the opto input is easily damaged.
The precidip connector used at SK1_X is a 1.27mm pitch connector that is unshrouded. When withdrawing the connector it is possible to accidentally bend the pins. When straightening the pins they often break. It is noted that this connector is not going to be fitted to the production fed. Any further use of this connector should be carefully considered.
|
| PR12 27-03-2003 (JS) |
It is noted that the power
and ground tracks for the opto device are small. This MAY result in problems in using the opto device. Measurements will be required once the opto device has been fitted. Better checks should be made at the layout stage.
|
| PR13 27-03-2003 (JS) |
2.2uF, 6.3 volt capacitors
have been used filtering the 5V optical stages. It is not good engineering practice to run a component at 80% of it’s maximum voltage. Any spike on the +/- 5V could cause one or more capacitors to go short circuit. These parts should be replaced by either GRM216R61A225KE24D this is a murata 10V 2.2uF X5R 0805 part, or GCM21BR71A105KC01L this a murata 10V 1.0uF X7R 0805 part. The effect of bias voltage on capacitance is modelled by software provided FOC by the Murata company.
|
| PR14 27-03-2003 (JS) |
It is noted that many
capacitors have been tracked and viaed rather than the via being very close
to the pad.
The pad and via need to be as close as possible to reduce the series inductance. The tracking of decoupling caps should be examined, for example C85 against C47
|
| PR15 27-03-2003 (JS) |
The front panel is shorting
the restart switch. The pins on the restart switch SW1 are too close to the front panel Move SW1 back from the front panel
|
| PR16 27-03-2003 (JS) |
U138 footprint is incorrect Due to an error the incorrect footprint was entered for this device. This still allowed the device to be fitted but reserved too much board area. This needs to be discussed with the DO and the footprint updated. The footprint should be corrected in the library, and the PCB revised with the new footprint. These switchers are also electrically noisy, this will be dealt with separately. Has been discussed with CD. A change request will be submitted.
|
| PR17 27-03-2003 (JS) |
Some ON card leds are lit
when the card is in an OK condition. The LED connections to U129 should be revised.
|
| PR18 27-03-2003 (JS) |
The connections to and the footprint of U135 are incorrect. There was no solder mask for the tab of U135 and the enable pin was tied high. See PR006 The footprint of this device needs correcting, and the connection to the enable pin needs tying low. The symbol should be revised with a bar over the EN. The use of the negation bubble should be discontinued except for standard logic symbols.
|
| PR19 27-03-2003 (JS) |
In some parts of the power
block 0402 and 0603 resistors have been used, but there was plenty of space
for larger parts. 0402 and 0603 passives are difficult to change. Where components may need to be changed 0805 should be used as preference.
|
| PR20 27-03-2003 (JS) |
It
is possible to short the board supply via the JTAG connector. It is possible to accidentally short the board by miss connecting the JTAG connector. It is suggested that a proper 2mm or 0.1in pitch connector is fitted, and that the Datamate series such as used on the signal injector card used.
|
| PR21 27-03-2003 (JS) |
Electrical noise
It is noted that the supply rails on the board contain a lot of electrical noise. This will be quantified once all the logic is in operation on the card.
|
| PR22 27-03-2003 (JS) |
The power supply can lock out
the board. When the board is subject to a gross under voltage condition it can lock out the supply indefinitely. To defeat this pin 8 on U128 has been lifted. This behaviour may be undesirable in a remote counting room, and needs to be considered further.
|
| PR23 27-03-2003 (JS) |
The track and via sizes on
the board are inconsistent. Examples D33, D34. D34 is a power diode intended to short the supply, the tracks will fuse before the supply trips out. The PCB designer needs to discuss with the design engineer likely current densities.
|
| PR24 27-03-2003 (JS EF) |
Electrical noise can cause a card reset. External radiated emissions can cause a reset of the card. It is suspected that it is picked up on the JTAG lines, also the floating watchdog line may be a suspect. On the next revision have some filters on the JTAG lines
|
| PR25 27-03-2003 (JS) |
3.3V rail is in over current trip after fitting opto devices 3.3 volts started tripping after fitting the opto devices. It is suspected that the 5V was propping up the 3.3V via the protection diodes on the analogue signal path. Problem resolved by fitting additional 0.005 ohm resistor R399 Current consumption will have to be monitored on the final firmware design.
|
| PR26 28-03-2003 (JS) |
Symbol for crystal is incorrect The symbol for the crystal U265 is incorrect. It does not show the shutdown pin. |
| PR27 6-5-2003 |
MAX5906 may fail to protect board There is a risk that under short circuit conditions the backplane voltage may collapse and the MAX5906 be unable to turn off it's FETs. Consider a different device or fuse backup, this problem managed to fuse the track to one of the protection diodes, see PR23
|
| PR28 6-5-2003 |
Feed back loop could cause cyclic tripping The PGO pin on the TP3510 is held high by a potential divider from 12VIN noise on the 12V could cause a glitch at the PGO pin, and cause a feedback loop The top of the divider can go to 5V sup, if 5V sup fails U133 goes off and inhibits supply, delete R1230
|
| PR29 |
12V switch can't run at full load The ripple caused by the action of the 12V to -5V switcher is causing the MAX5906 part to trip at startup. Suggest fitting a filter such as a 15uH choke to reduce the supply current ripple. This requires further investigation with a 50MHz bandwidth probe.
|
| PR30 |
Some tantalum capacitors have a self
resonant frequency of 500KHz or less.
Not an issue?
|
| PR31
22 May 2003 SAB |
Voltage on QDR SRAM JTAG port exceeds datasheet specification.
I cannot see any level translators or open collector outputs with pull ups to 2v5 to drive the JTAG inputs to the QDRs (u99, u100). The relevant spec is given below.
I have been through this problem with Saeed T. He has shown me the circuits and I do not believe that there is any electronic problem. All the circuit details are spread out and must be considered to see the complete picture. If there is any problem it is the cumbersome and hard to review circuit diagram.
|
| PR32 |
Contention problem GRANT_SWAP# R6 and RN36 can contend, circuit revision required. The following need to be renamed VME_GRANT_SWAP# to SWAP_GRANTED GRANT_SWAP# to GRANT_SWAP SWAP_REQ# to SWAP_REQ on U123 and PL19 SWAP_RQ# to SWAP-RQ (U123 Pn 10-A) & (U107 pin N6) Connect R339 to GND instead of 5VSUP Connect PL20 to 5VSUP instead of GND
|
| PR33 |
Mat Noy reports CH5 in each module is noisy Suspect a problem with the decoupling cap associated with CH5 (in s/w readout numbering scheme) This corresponds to 2nd FED_ADC module I41 ; Bottom ADC chan B = BOT_DB ; from OPTOD
|
| PR34 |
Gate oscillations seen at U142 Suspect this is due to U142 being a logic level fet. Suggest replacing with a IRFZ24NS This part has a higher threshold voltage 4V compared to 2 volts, also has 10% of the intergate capacitance than the IRL3705NS
|
| PR35 |
Various minor improvements, To improve the reset performance the following changes should be made Discharge resistors fitted to power planes, 1.5V 1Kohm, 2.5v 1kOhm, 3.3V 1Kohm 5V 1Kohm and 12V 5.6k. A 47CT0205 diode to be fitted in parallel with C789 (220uF 10v), anode to 5Vneg, this is to reduce the swing on 5V neg when the 12V to -5 switcher is off. There are several LED errors TSHDOWN led sense needs reversing, remove existing connection between R429 and U129 (HEF40240BT) pin8 Connect R429 and pin 12. Calice would like Leds to come on in the Active condition; R1221 R1222, R1223, R1225, R1226, R1227, R1228 dis connect Pin 2 from GND and connect to 5VSUP R1224 connect disconnect pin2 from GND and connect to 5VSUP, Rotate DS81 to D88.
|
| PR36 |
Peaking caps have been fitted to the opto stage, dispite being marked as DO
NOT fit.
Peaking caps have been fitted to the opto stage, dispite being marked as DO NOT fit, on both the schematics and the assembly instructions. They are present on the top of #1 and #2, the whole of #3 and #5. #4 needs to be checked.
|
| PR37
(ST) |
TTC does not reset correctly when power is tripped on the board, need to
investigate reset to the TTCRX BGA
|
|
PR38 (ST) |
Possible short duration signal conflict.
The input and tri-state enable pins on a number of 74LVTH125 chips are connected to the same signal such that the device output is only pulled to ground when input signal is low and tri-stated when input signal is high. The output of the following ICs go to the VME back plane and therefore is connected to the outputs from other drivers on other FED cards. This situation has a condition such that the input is propagated to the output pin before the tri-state pin disables the output. Therefore the condition exists for a very short period of time that one diver could be pulling low while another is driving high. On all these devices with the above condition, the input pin must be connected to ground (via a resistor) and the tri-state pin must be connected to the desired signal, therefore removing the condition when the output signal is driven high before it is disabled. These devices are: U1, U122, U123, U266.
|
| PR39 (ST) |
Some Virtex II devices use ALT_VRN &
ALT_VRP pins as the DCI pins.
This requires a global variable to be used which forces all Virtex II devices to use ALT_VRN & ALT_VRP pins. Change the schematic such that normal VRN & VRP pins are used for DCI.
|
| PR40 (ST) |
SLINK signal LDOWN#
It is required by SLINK specification that the signal LDOWN# is pulled down on the Front End Motherboard if Link Source Card is not plugged in or powered down. Add pull down resistor 4K7 0402 to signal SLINK_LDOWN# on pin 4D of J2 (PL18) connector. Immediate Action: Internal pull up resistor on the BACK END FPGA enabled on this pin.
|
| PR41 (IC) 01.10.2003 |
Incorrect position of the OPTO fixing holes. |
|
PR42 JC |
Pre-pulse undershoot of AD9218 in 2Vpp mode
Operate in 1Vpp mode and add 100 Ohm resistor across ADC inputs.
|
|
PR43 CPD |
Changing PCB manufacturer.
The PCB is being made by another Board Manufacturer and they can’t achieve the same impedances with the existing board build. To achieve the closest impedance figures to the original design the track widths will have to change, as well as the specified impedance figures.
|
| PR44 (ST) |
Provide ground bars on the FED V2.
|
| PR45 (ST) |
Add DO NOT FIT to SLINK signals LDVS termination resistors: R1212, R1213, R1214, R1215.
|
| PR46 (ST) 26/07/2004 |
Add 1k0 resistor to VCC to pin 16 of the voltage monitor device U136 ADM1025A . This pin is sampled on power up to determine device address, this resistor will ensure the pin is held at 3.3V on power up, so the device address is registered as "01".
|
| PR47 (ST) 26/07/2004 |
Add 10k resistor to GND to pin 9 of the voltage monitor device U136 ADM1025A . This pin is sampled on power up to determine if a NAND Tree Test is required. If this pin is high then the NAND Tree Test mode is activated.
|
| PR48 (JC) 23.03.2004 |
TTC bushing presses on C116_5. Replace all C116_n with lower profile part. |
| PR49 (JC) 23.03.2004 |
Some TTC chanB signals were left off. Adding should make firmware simpler. Connect Dout<7:0>, DQ<3:0> and DOUTSTR to BE FPGA. |
| PR50 (JC) 23.03.2004 |
QDRI 9Mb is obsolete. Change to QDRII part as used by CALICE. Change Linear to supply new Vdd 1.8V?
|
| PR51 (JC) 23.03.2004 |
XICOR EPROM is obsolete. No action. Enough stock in hand. |
| PR52 (JC) 23.03.2004 |
REF191GRU TSSOP is obsolete. Buy stock or switch to SOIC package. |
| PR53 (JC) 23.03.2004 |
Reflections observed on S-LINK clock on Transition card. Drive S-LINK clock out differentially. |
| PR54 (JC) 23.03.2004 |
Proposed Transition card only connects to J2. Adopt Greg Iles's proposal. This assumes TTS signals are suitably converted for FMM on Transition card.
|
| PR55 (JC) 23.03.2004 |
Protruding leads of U139 (5V->1.5V) snag on neighbouring boards. Trim leads. |
| PR56 (JC) 30.03.2004 |
LEDs on Delay FPGA (and elsewhere?) shorting. Increase footprints, or use smaller LEDs. |
| PR57 (JC) 31.03.2004 |
Imperial College measurements show heat dissipation concentrated along Front of board. Stretch FE channel circuit after Elantec Opamp buffer. |
| PR58 (JC) 31.03.2004 |
Paulo Moreira CERN comments on TTCrx circuit. JTAGTRST_B [pin M2]must be tied to Gnd during normal operation. (and needs modifying to be compatible with BScan testing) . This change cures problems with TTCrx starting up in BAD state with "TTC Ready" signal permanently true. Tie PROMD [pin C1] to GND (PROM is not used on FED).
|
| PR59 (ST) 27.04..2004 |
Add System ACE to the Configuration JTAG Chain. Remove System ACE from the VME JTAG chain and add to System ACE JTAG chain. |
| PR60 (JC) 30.04.2004 |
Implement recommendations from DDi
Report where practicable. E.g. pad sizes, fiducials, assembly notes. |
| PR61 (JC) 30.04.2004 |
Add additional holes for mounting air deflector / strengthening bars. |
| PR62 (ST) 30.04.2004 |
When a FED was inserted into a crate with other FEDs, it caused a reset on
the other FEDs already in the crate. This was traced to a dip in voltage on the +12VIN supply caused by capacitor C3399 100nF. This may be due to low break down voltage of this capacitor. Must investigate the type of capacitor and replace it with another which can withstand the 12V.
|
| PR63 (ST) 30.04.2004 |
When a FED is inserted into a powered up crate, it does not start up in a
normal manner and the blue LED turns on and stays on until the reset button
on the front panel is pressed. This was investigated and the following results were found: When board is first inserted the +5V gets connected and through LM393 (U127) signal PSON# is pulsed high and then low. This happens before the +12VIN is present. Then after the board has been inserted into the crate and all supplies are present, TPS3510 (U128) holds signal PGO low. This signal in turn causes 5V_12V_EN to go low and disable power to the board. To rectify: Modify the V2 schematics such that +1V5 is the last power which is enabled on the board. Therefore PSON# is pulsed high after all input supplies are present and stable.
|
| PR64 (JC) 03.06.2004 |
Front Panel changes for FEDv2
1. Holes in Front Panel need enlarging for OptoRx. Jan Troska CERN The left-hand side of the hole (looking at the FED) needs to be increased by at least 1mm to allow the QR-code label in the MPO connector to pass unhindered. 2. Labelling of OptoRx changed to match cable numbering. Francois Vasey CERN Number the FED inputs from 1 (bottom) to 8 (top). |
