Saeed's FED Clock
Timing Distribution document (incl TTCrx variations) For Test Results refer to Route Cards pages
Testing Procedures at the Assembly Company Latest Document
RAL Acceptance Testing Document
FEDv2 Channel Numbering vs Component Designators (xls)
Ivan's colour coded FE Analogue layout
Original Test Plan
Testing without inputs Draft Document (Matt Noy)
Mark Raymond's mods to FEDv1 nr 002 for Front-End Analogue component tuning.
Cross-Talk results
Analogue
Characterisation studies Report by Stefanos Dris
Timing
Timing Delay FPGA Fine Skew Measurements
Saeed's FED Clock
Timing Distribution document (incl TTCrx variations)
JTAG Boundary Scan
JTAG Technologies home page
JTAG product summaries