README file: Virtex-II Platform FPGA Handbook
=============================================

Date: March, 2001

VHDL code examples are provided to illustrate the Chapter 2 - Design Considerations - of 
the Virtex-II Platform FPFA Handbook.

- VHDL Templates:
VHDL templates are available as examples to instantiate primitives. 
Each template has a component declaration section and an architecture section. 
Each part of the template should be inserted within the VHDL design file. 
The portmap of the architecture section should include the design signal names.

- VHDL Submodules:
VHDL submodules are low level VHDL code instantiating some primitives. 
These submodules can be instantiated in a design and must be synthesized with the design.

The templates and submodules can be found in the following directories corresponding to 
each section of the Chapter 2: Design Considerations (Virtex-II Platform FPGA HandBook)

Directory:
------------

- multipliers: "Using Embedded Multipliers"

Templates (primitive):
 MULT18X18.vhd

Submodules (code example):
 mult17x17.vhd
 mult4x4_s.vhd
 mult4x4_u.vhd
 mult8x8_s.vhd
 mult8x8_u.vhd
 signed_mult18x18.vhd
 signed_mult_4x4_rr.vhd
 signed_mult_8x8_rr.vhd
 unsigned_mult_17x17_rr.vhd
 unsigned_mult_8x8_rr.vhd
 unsigned_mult_8x8_rr.vhd
 

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