README file: Virtex-II Platform FPGA Handbook
=============================================

Date: March, 2001

VHDL code examples are provided to illustrate the Chapter 2 - Design Considerations - of 
the Virtex-II Platform FPFA Handbook.

- VHDL Templates:
VHDL templates are available as examples to instantiate primitives. 
Each template has a component declaration section and an architecture section. 
Each part of the template should be inserted within the VHDL design file. 
The portmap of the architecture section should include the design signal names.

- VHDL Submodules:
VHDL submodules are low level VHDL code instantiating some primitives. 
These submodules can be instantiated in a design and must be synthesized with the design.

The templates and submodules can be found in the following directories corresponding to 
each section of the Chapter 2: Design Considerations (Virtex-II Platform FPGA HandBook)

Directory:
------------

- distributed_ram: "Using Distributed SelectRAM Memory"

Templates (primitive):
 SELECTRAM_16S
 SELECTRAM_32S
 SELECTRAM_64S
 SELECTRAM_128S
 SELECTRAM_16D
 SELECTRAM_32D
 SELECTRAM_64D

Submodules (code example):
 XC2V_RAM16XN_S_SUBM
 XC2V_RAM32XN_S_SUBM
 XC2V_RAM64XN_S_SUBM
 XC2V_RAM128XN_S_SUBM
 XC2V_RAM16XN_D_SUBM
 XC2V_RAM32XN_D_SUBM
 XC2V_RAM64XN_D_SUBM

Example with initialisation:
 XC2V_DISTRI_RAM_64S

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