README file: Virtex-II Platform FPGA Handbook
=============================================

Date: March, 2001

VHDL code examples are provided to illustrate the Chapter 2 - Design Considerations - of 
the Virtex-II Platform FPFA Handbook.

- VHDL Templates:
VHDL templates are available as examples to instantiate primitives. 
Each template has a component declaration section and an architecture section. 
Each part of the template should be inserted within the VHDL design file. 
The portmap of the architecture section should include the design signal names.

- VHDL Submodules:
VHDL submodules are low level VHDL code instantiating some primitives. 
These submodules can be instantiated in a design and must be synthesized with the design.

The templates and submodules can be found in the following directories corresponding to each section of 
the Chapter 2: Design Considerations (Virtex-II Platform FPGA HandBook)

Directory:
------------

- blockram: "Using Block SelectRAM Memory"

Templates (primitive):
 
 Single-port templates:
  SelectRAM_A1
  SelectRAM_A2
  SelectRAM_A4
  SelectRAM_A9
  SelectRAM_A18
  SelectRAM_A36

 Dual-port templates:
  SelectRAM_A1_B1
  SelectRAM_A1_B2
  SelectRAM_A1_B4
  SelectRAM_A1_B9
  SelectRAM_A1_B18
  SelectRAM_A1_B36
  SelectRAM_A2_B2
  SelectRAM_A2_B4
  SelectRAM_A2_B9
  SelectRAM_A2_B18
  SelectRAM_A2_B36
  SelectRAM_A4_B4
  SelectRAM_A4_B9
  SelectRAM_A4_B18
  SelectRAM_A4_B36
  SelectRAM_A9_B9
  SelectRAM_A9_B18
  SelectRAM_A9_B36
  SelectRAM_A18_B18
  SelectRAM_A18_B36
  SelectRAM_A36_B36

Example:
 XC2V_RAMB_1_PORT


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