DocumentHdrVersion "1.1"
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library "ieee"
unitName "std_logic_1164"
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library "ieee"
unitName "std_logic_arith"
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version "16.1"
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variable "HDSDir"
value "D:\\CMS_FED\\VME_FPGA\\hds"
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variable "SideDataDesignDir"
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(vvPair
variable "appl"
value "HDL Designer"
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value "interface"
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variable "config"
value "%(unit)_config"
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variable "d"
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variable "d_logical"
value "D:\\CMS_FED\\VME_FPGA\\hds\\tst_lm82"
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value "07/09/2004"
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variable "dd"
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variable "entity_name"
value "tst_lm82"
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variable "library_downstream_ModelSimCompiler"
value "D:/CMS_FED/VME_FPGA/sim"
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variable "library_downstream_PrecisionSynthesisDataPrep"
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(vvPair
variable "mm"
value "09"
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variable "module_name"
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(vvPair
variable "month"
value "Sep"
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variable "month_long"
value "September"
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variable "p"
value "D:\\CMS_FED\\VME_FPGA\\hds\\tst_lm82\\interface"
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variable "p_logical"
value "D:\\CMS_FED\\VME_FPGA\\hds\\tst_lm82\\interface"
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variable "project_name"
value "CMS_FED"
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(vvPair
variable "series"
value "HDL Designer Series"
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(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
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variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "$HDS_HOME/../Modeltech/win32"
)
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variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "$HDS_HOME/../Precision/Mgc_home/bin"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "time"
value "11:11:02"
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(vvPair
variable "unit"
value "tst_lm82"
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(vvPair
variable "user"
value "st79"
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(vvPair
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