DocumentHdrVersion "1.1"
Header (DocumentHdr
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "std_logic_arith"
)
(DmPackageRef
library "UNISIM"
unitName "all"
itemName ""
)
]
)
version "16.1"
appVersion "2003.2 (Build 28)"
model (Symbol
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vvMap [
(vvPair
variable "HDLDir"
value "D:\\CMS_FED\\VME_FPGA\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\CMS_FED\\VME_FPGA\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\CMS_FED\\VME_FPGA\\hds\\bus_error\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\CMS_FED\\VME_FPGA\\hds\\bus_error\\interface.user"
)
(vvPair
variable "SourceDir"
value "D:\\CMS_FED\\VME_FPGA\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "interface"
)
(vvPair
variable "config"
value "%(unit)_config"
)
(vvPair
variable "d"
value "D:\\CMS_FED\\VME_FPGA\\hds\\bus_error"
)
(vvPair
variable "d_logical"
value "D:\\CMS_FED\\VME_FPGA\\hds\\bus_error"
)
(vvPair
variable "date"
value "22/09/2004"
)
(vvPair
variable "day"
value "Wed"
)
(vvPair
variable "day_long"
value "Wednesday"
)
(vvPair
variable "dd"
value "22"
)
(vvPair
variable "entity_name"
value "bus_error"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "interface"
)
(vvPair
variable "f_logical"
value "interface"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "TE2MALDIVES"
)
(vvPair
variable "library"
value "vme_firmware"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "D:/CMS_FED/VME_FPGA/sim"
)
(vvPair
variable "library_downstream_PrecisionSynthesisDataPrep"
value "D:/CMS_FED/VME_FPGA/ps"
)
(vvPair
variable "mm"
value "09"
)
(vvPair
variable "module_name"
value "bus_error"
)
(vvPair
variable "month"
value "Sep"
)
(vvPair
variable "month_long"
value "September"
)
(vvPair
variable "p"
value "D:\\CMS_FED\\VME_FPGA\\hds\\bus_error\\interface"
)
(vvPair
variable "p_logical"
value "D:\\CMS_FED\\VME_FPGA\\hds\\bus_error\\interface"
)
(vvPair
variable "project_name"
value "CMS_FED"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "$HDS_HOME/../Modeltech/win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "$HDS_HOME/../Precision/Mgc_home/bin"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "time"
value "11:32:26"
)
(vvPair
variable "unit"
value "bus_error"
)
(vvPair
variable "user"
value "st79"
)
(vvPair
variable "version"
value "2003.2 (Build 28)"
)
(vvPair
variable "view"
value "interface"
)
(vvPair
variable "year"
value "2004"
)
(vvPair
variable "yy"
value "04"
)
]
)
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