DocumentHdrVersion "1.1"
Header (DocumentHdr
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "std_logic_arith"
)
(DmPackageRef
library "IEEE"
unitName "VITAL_Timing"
)
(DmPackageRef
library "IEEE"
unitName "VITAL_Primitives"
)
]
)
version "16.1"
appVersion "2003.2 (Build 28)"
model (Symbol
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "D:\\CMS_FED\\vme_firmware\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\CMS_FED\\vme_firmware\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\CMS_FED\\vme_firmware\\hds\\ace_reg_decoder\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\CMS_FED\\vme_firmware\\hds\\ace_reg_decoder\\interface.user"
)
(vvPair
variable "SourceDir"
value "D:\\CMS_FED\\vme_firmware\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "interface"
)
(vvPair
variable "config"
value "%(unit)_config"
)
(vvPair
variable "d"
value "D:\\CMS_FED\\vme_firmware\\hds\\ace_reg_decoder"
)
(vvPair
variable "d_logical"
value "D:\\CMS_FED\\vme_firmware\\hds\\ace_reg_decoder"
)
(vvPair
variable "date"
value "21/09/2005"
)
(vvPair
variable "day"
value "Wed"
)
(vvPair
variable "day_long"
value "Wednesday"
)
(vvPair
variable "dd"
value "21"
)
(vvPair
variable "entity_name"
value "ace_reg_decoder"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "interface"
)
(vvPair
variable "f_logical"
value "interface"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "TE2MALDIVES"
)
(vvPair
variable "library"
value "vme_firmware"
)
(vvPair
variable "library_downstream_LeonardoSpectrum"
value "D:\\CMS_FED\\vme_firmware\\ls"
)
(vvPair
variable "library_downstream_LeonardoSpectrum(GUI)"
value "D:\\CMS_FED\\vme_firmware\\ls"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\CMS_FED\\vme_firmware\\sim"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "D:/CMS_FED/vme_firmware/sim"
)
(vvPair
variable "library_downstream_PrecisionSynthesisDataPrep"
value "D:/CMS_FED/vme_firmware/ps"
)
(vvPair
variable "mm"
value "09"
)
(vvPair
variable "module_name"
value "ace_reg_decoder"
)
(vvPair
variable "month"
value "Sep"
)
(vvPair
variable "month_long"
value "September"
)
(vvPair
variable "p"
value "D:\\CMS_FED\\vme_firmware\\hds\\ace_reg_decoder\\interface"
)
(vvPair
variable "p_logical"
value "D:\\CMS_FED\\vme_firmware\\hds\\ace_reg_decoder\\interface"
)
(vvPair
variable "project_name"
value "CMS_FED"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "$HDS_HOME/../Modeltech/win32"
)
(vvPair
variable "task_NC"
value "<TBD>"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "$HDS_HOME/../Precision/Mgc_home/bin"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "time"
value "09:49:01"
)
(vvPair
variable "unit"
value "ace_reg_decoder"
)
(vvPair
variable "user"
value "st79"
)
(vvPair
variable "version"
value "2003.2 (Build 28)"
)
(vvPair
variable "view"
value "interface"
)
(vvPair
variable "year"
value "2005"
)
(vvPair
variable "yy"
value "05"
)
]
)
uid 71,0
optionalChildren [
*1 (SymbolBody
uid 8,0
optionalChildren [
*2 (CptPort
uid 977,0
ps "OnEdgeStrategy"
shape (Triangle
uid 978,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,10625,15000,11375"
)
n "addr_from_vme"
t "std_logic_VECTOR"
b "(15 DOWNTO 0)"
o 4
r 1
tg (CPTG
uid 979,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 980,0
va (VaSet
)
xt "16000,10500,21900,11500"
st "addr_from_vme"
blo "16000,11300"
tm "CptPortNameMgr"
)
s (Text
uid 981,0
va (VaSet
)
xt "16000,11500,29800,12500"
st "std_logic_VECTOR(15 DOWNTO 0)"
blo "16000,12300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 982,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2000,75500,2800"
st "addr_from_vme     : IN     std_logic_VECTOR (15 DOWNTO 0) ;
"
)
)
*3 (CptPort
uid 983,0
ps "OnEdgeStrategy"
shape (Triangle
uid 984,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,14625,15000,15375"
)
n "clk"
t "std_logic"
o 5
r 2
tg (CPTG
uid 985,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 986,0
va (VaSet
)
xt "16000,14500,16900,15500"
st "clk"
blo "16000,15300"
tm "CptPortNameMgr"
)
s (Text
uid 987,0
va (VaSet
)
xt "16000,15500,19100,16500"
st "std_logic"
blo "16000,16300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 988,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2800,65000,3600"
st "clk               : IN     std_logic  ;
"
)
)
*4 (CptPort
uid 989,0
ps "OnEdgeStrategy"
shape (Triangle
uid 990,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,12625,15000,13375"
)
n "data_rdy_1"
t "std_logic"
o 2
r 3
tg (CPTG
uid 991,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 992,0
va (VaSet
)
xt "16000,12500,20400,13500"
st "data_rdy_1"
blo "16000,13300"
tm "CptPortNameMgr"
)
s (Text
uid 993,0
va (VaSet
)
xt "16000,13500,19100,14500"
st "std_logic"
blo "16000,14300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 994,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3600,65000,4400"
st "data_rdy_1        : IN     std_logic  ;
"
)
)
*5 (CptPort
uid 995,0
ps "OnEdgeStrategy"
shape (Triangle
uid 996,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,6625,25750,7375"
)
n "en_bus_mode_reg"
t "std_logic"
m 1
o 5
r 5
tg (CPTG
uid 997,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 998,0
va (VaSet
)
xt "17000,6500,24000,7500"
st "en_bus_mode_reg"
ju 2
blo "24000,7300"
tm "CptPortNameMgr"
)
s (Text
uid 999,0
va (VaSet
)
xt "20900,7500,24000,8500"
st "std_logic"
ju 2
blo "24000,8300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1000,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5200,65000,6000"
st "en_bus_mode_reg   : OUT    std_logic  ;
"
)
)
*6 (CptPort
uid 1001,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1002,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,14625,25750,15375"
)
n "en_cfg_lbareg_lsb"
t "std_logic"
m 1
o 5
r 6
tg (CPTG
uid 1003,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1004,0
va (VaSet
)
xt "16900,14500,24000,15500"
st "en_cfg_lbareg_lsb"
ju 2
blo "24000,15300"
tm "CptPortNameMgr"
)
s (Text
uid 1005,0
va (VaSet
)
xt "20900,15500,24000,16500"
st "std_logic"
ju 2
blo "24000,16300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1006,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6000,65000,6800"
st "en_cfg_lbareg_lsb : OUT    std_logic  ;
"
)
)
*7 (CptPort
uid 1007,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1008,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,15625,25750,16375"
)
n "en_cfg_lbareg_msb"
t "std_logic"
m 1
o 5
r 7
tg (CPTG
uid 1009,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1010,0
va (VaSet
)
xt "16500,15500,24000,16500"
st "en_cfg_lbareg_msb"
ju 2
blo "24000,16300"
tm "CptPortNameMgr"
)
s (Text
uid 1011,0
va (VaSet
)
xt "20900,16500,24000,17500"
st "std_logic"
ju 2
blo "24000,17300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1012,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6800,65000,7600"
st "en_cfg_lbareg_msb : OUT    std_logic  ;
"
)
)
*8 (CptPort
uid 1013,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1014,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,23625,25750,24375"
)
n "en_cntl_reg_lsb"
t "std_logic"
m 1
o 5
r 8
tg (CPTG
uid 1015,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1016,0
va (VaSet
)
xt "17800,23500,24000,24500"
st "en_cntl_reg_lsb"
ju 2
blo "24000,24300"
tm "CptPortNameMgr"
)
s (Text
uid 1017,0
va (VaSet
)
xt "20900,24500,24000,25500"
st "std_logic"
ju 2
blo "24000,25300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1018,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7600,65000,8400"
st "en_cntl_reg_lsb   : OUT    std_logic  ;
"
)
)
*9 (CptPort
uid 1019,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1020,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,24625,25750,25375"
)
n "en_cntl_reg_msb"
t "std_logic"
m 1
o 5
r 9
tg (CPTG
uid 1021,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1022,0
va (VaSet
)
xt "17400,24500,24000,25500"
st "en_cntl_reg_msb"
ju 2
blo "24000,25300"
tm "CptPortNameMgr"
)
s (Text
uid 1023,0
va (VaSet
)
xt "20900,25500,24000,26500"
st "std_logic"
ju 2
blo "24000,26300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1024,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8400,65000,9200"
st "en_cntl_reg_msb   : OUT    std_logic  ;
"
)
)
*10 (CptPort
uid 1025,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1026,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,11625,25750,12375"
)
n "en_error_reg_lsb"
t "std_logic"
m 1
o 5
r 10
tg (CPTG
uid 1027,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1028,0
va (VaSet
)
xt "17300,11500,24000,12500"
st "en_error_reg_lsb"
ju 2
blo "24000,12300"
tm "CptPortNameMgr"
)
s (Text
uid 1029,0
va (VaSet
)
xt "20900,12500,24000,13500"
st "std_logic"
ju 2
blo "24000,13300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1030,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,9200,65000,10000"
st "en_error_reg_lsb  : OUT    std_logic  ;
"
)
)
*11 (CptPort
uid 1031,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1032,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,12625,25750,13375"
)
n "en_error_reg_msb"
t "std_logic"
m 1
o 5
r 11
tg (CPTG
uid 1033,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1034,0
va (VaSet
)
xt "16900,12500,24000,13500"
st "en_error_reg_msb"
ju 2
blo "24000,13300"
tm "CptPortNameMgr"
)
s (Text
uid 1035,0
va (VaSet
)
xt "20900,13500,24000,14500"
st "std_logic"
ju 2
blo "24000,14300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1036,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10000,65000,10800"
st "en_error_reg_msb  : OUT    std_logic  ;
"
)
)
*12 (CptPort
uid 1037,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1038,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,26625,25750,27375"
)
n "en_fatstat_reg"
t "std_logic"
m 1
o 5
r 12
tg (CPTG
uid 1039,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1040,0
va (VaSet
)
xt "18400,26500,24000,27500"
st "en_fatstat_reg"
ju 2
blo "24000,27300"
tm "CptPortNameMgr"
)
s (Text
uid 1041,0
va (VaSet
)
xt "20900,27500,24000,28500"
st "std_logic"
ju 2
blo "24000,28300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1042,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10800,65000,11600"
st "en_fatstat_reg    : OUT    std_logic  ;
"
)
)
*13 (CptPort
uid 1043,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1044,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,17625,25750,18375"
)
n "en_mpu_lbareg_lsb"
t "std_logic"
m 1
o 5
r 13
tg (CPTG
uid 1045,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1046,0
va (VaSet
)
xt "16600,17500,24000,18500"
st "en_mpu_lbareg_lsb"
ju 2
blo "24000,18300"
tm "CptPortNameMgr"
)
s (Text
uid 1047,0
va (VaSet
)
xt "20900,18500,24000,19500"
st "std_logic"
ju 2
blo "24000,19300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1048,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,11600,65000,12400"
st "en_mpu_lbareg_lsb : OUT    std_logic  ;
"
)
)
*14 (CptPort
uid 1049,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1050,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,18625,25750,19375"
)
n "en_mpu_lbareg_msb"
t "std_logic"
m 1
o 5
r 14
tg (CPTG
uid 1051,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1052,0
va (VaSet
)
xt "16200,18500,24000,19500"
st "en_mpu_lbareg_msb"
ju 2
blo "24000,19300"
tm "CptPortNameMgr"
)
s (Text
uid 1053,0
va (VaSet
)
xt "20900,19500,24000,20500"
st "std_logic"
ju 2
blo "24000,20300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1054,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,12400,65000,13200"
st "en_mpu_lbareg_msb : OUT    std_logic  ;
"
)
)
*15 (CptPort
uid 1055,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1056,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,20625,25750,21375"
)
n "en_seccntcmd_reg"
t "std_logic"
m 1
o 5
r 15
tg (CPTG
uid 1057,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1058,0
va (VaSet
)
xt "16800,20500,24000,21500"
st "en_seccntcmd_reg"
ju 2
blo "24000,21300"
tm "CptPortNameMgr"
)
s (Text
uid 1059,0
va (VaSet
)
xt "20900,21500,24000,22500"
st "std_logic"
ju 2
blo "24000,22300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1060,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,13200,65000,14000"
st "en_seccntcmd_reg  : OUT    std_logic  ;
"
)
)
*16 (CptPort
uid 1061,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1062,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,8625,25750,9375"
)
n "en_status_reg_lsb"
t "std_logic"
m 1
o 5
r 16
tg (CPTG
uid 1063,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1064,0
va (VaSet
)
xt "17000,8500,24000,9500"
st "en_status_reg_lsb"
ju 2
blo "24000,9300"
tm "CptPortNameMgr"
)
s (Text
uid 1065,0
va (VaSet
)
xt "20900,9500,24000,10500"
st "std_logic"
ju 2
blo "24000,10300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1066,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14000,65000,14800"
st "en_status_reg_lsb : OUT    std_logic  ;
"
)
)
*17 (CptPort
uid 1067,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1068,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,9625,25750,10375"
)
n "en_status_reg_msb"
t "std_logic"
m 1
o 5
r 17
tg (CPTG
uid 1069,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1070,0
va (VaSet
)
xt "16600,9500,24000,10500"
st "en_status_reg_msb"
ju 2
blo "24000,10300"
tm "CptPortNameMgr"
)
s (Text
uid 1071,0
va (VaSet
)
xt "20900,10500,24000,11500"
st "std_logic"
ju 2
blo "24000,11300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1072,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14800,65000,15600"
st "en_status_reg_msb : OUT    std_logic  ;
"
)
)
*18 (CptPort
uid 1073,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1074,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "25000,21625,25750,22375"
)
n "en_version_reg"
t "std_logic"
m 1
o 5
r 18
tg (CPTG
uid 1075,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1076,0
va (VaSet
)
xt "18000,21500,24000,22500"
st "en_version_reg"
ju 2
blo "24000,22300"
tm "CptPortNameMgr"
)
s (Text
uid 1077,0
va (VaSet
)
xt "20900,22500,24000,23500"
st "std_logic"
ju 2
blo "24000,23300"
tm "CptPortTypeMgr"
)
)
dt (MLText
uid 1078,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,15600,64000,16400"
st "en_version_reg    : OUT    std_logic 
"
)
)
*19 (CptPort
uid 1079,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1080,0
ro 90
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