DocumentHdrVersion "1.1"
Header (DocumentHdr
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "std_logic_arith"
)
(DmPackageRef
library "IEEE"
unitName "VITAL_Timing"
)
(DmPackageRef
library "IEEE"
unitName "VITAL_Primitives"
)
]
)
version "16.1"
appVersion "2003.2 (Build 28)"
model (Symbol
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "D:\\CMS_FED\\VME_FPGA\\hdl"
)
(vvPair
variable "HDSDir"
value "D:\\CMS_FED\\VME_FPGA\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "D:\\CMS_FED\\VME_FPGA\\hds\\ace_controller\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "D:\\CMS_FED\\VME_FPGA\\hds\\ace_controller\\interface.user"
)
(vvPair
variable "SourceDir"
value "D:\\CMS_FED\\VME_FPGA\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "interface"
)
(vvPair
variable "config"
value "%(unit)_config"
)
(vvPair
variable "d"
value "D:\\CMS_FED\\VME_FPGA\\hds\\ace_controller"
)
(vvPair
variable "d_logical"
value "D:\\CMS_FED\\VME_FPGA\\hds\\ace_controller"
)
(vvPair
variable "date"
value "25/08/2004"
)
(vvPair
variable "day"
value "Wed"
)
(vvPair
variable "day_long"
value "Wednesday"
)
(vvPair
variable "dd"
value "25"
)
(vvPair
variable "entity_name"
value "ace_controller"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "interface"
)
(vvPair
variable "f_logical"
value "interface"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "TE2MOZAMBIQUE"
)
(vvPair
variable "library"
value "vme_firmware"
)
(vvPair
variable "library_downstream_LeonardoSpectrum"
value "D:\\CMS_FED\\vme_firmware\\ls"
)
(vvPair
variable "library_downstream_LeonardoSpectrum(GUI)"
value "D:\\CMS_FED\\vme_firmware\\ls"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\CMS_FED\\vme_firmware\\sim"
)
(vvPair
variable "mm"
value "08"
)
(vvPair
variable "module_name"
value "ace_controller"
)
(vvPair
variable "month"
value "Aug"
)
(vvPair
variable "month_long"
value "August"
)
(vvPair
variable "p"
value "D:\\CMS_FED\\VME_FPGA\\hds\\ace_controller\\interface"
)
(vvPair
variable "p_logical"
value "D:\\CMS_FED\\VME_FPGA\\hds\\ace_controller\\interface"
)
(vvPair
variable "project_name"
value "CMS_FED"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "$HDS_HOME/../Modeltech/win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "$HDS_HOME/../Precision/Mgc_home/bin"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "time"
value "16:47:15"
)
(vvPair
variable "unit"
value "ace_controller"
)
(vvPair
variable "user"
value "st79"
)
(vvPair
variable "version"
value "2003.2 (Build 28)"
)
(vvPair
variable "view"
value "interface"
)
(vvPair
variable "year"
value "2004"
)
(vvPair
variable "yy"
value "04"
)
]
)
uid 121,0
optionalChildren [
*1 (SymbolBody
uid 8,0
optionalChildren [
*2 (CptPort
uid 1504,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1505,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,13625,15000,14375"
)
n "ace_clk_int"
t "std_logic"
o 9
r 1
tg (CPTG
uid 1506,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1507,0
va (VaSet
)
xt "16000,13500,20500,14500"
st "ace_clk_int"
blo "16000,14300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1508,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2000,64500,2800"
st "ace_clk_int      : IN     std_logic  ;
"
)
)
*3 (CptPort
uid 1509,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1510,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,15625,15000,16375"
)
n "ace_cntl_data_en"
t "std_logic"
o 5
r 2
tg (CPTG
uid 1511,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1512,0
va (VaSet
)
xt "16000,15500,22600,16500"
st "ace_cntl_data_en"
blo "16000,16300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1513,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2800,64500,3600"
st "ace_cntl_data_en : IN     std_logic  ;
"
)
)
*4 (CptPort
uid 1514,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1515,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,18625,15000,19375"
)
n "ACE_data_to_vme"
t "std_logic_vector"
b "(31 DOWNTO 0)"
m 1
o 6
r 11
tg (CPTG
uid 1516,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1517,0
va (VaSet
)
xt "16000,18500,22900,19500"
st "ACE_data_to_vme"
blo "16000,19300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1518,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10000,75000,10800"
st "ACE_data_to_vme  : OUT    std_logic_vector (31 DOWNTO 0) ;
"
)
)
*5 (CptPort
uid 1519,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1520,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,12625,15000,13375"
)
n "cf_rdy_bsy_B"
t "std_logic"
o 12
r 3
tg (CPTG
uid 1521,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1522,0
va (VaSet
)
xt "16000,12500,21200,13500"
st "cf_rdy_bsy_B"
blo "16000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1523,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3600,64500,4400"
st "cf_rdy_bsy_B     : IN     std_logic  ;
"
)
)
*6 (CptPort
uid 1524,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1525,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,20625,15000,21375"
)
n "clk"
t "std_logic"
o 5
r 4
tg (CPTG
uid 1526,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1527,0
va (VaSet
)
xt "16000,20500,16900,21500"
st "clk"
blo "16000,21300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1528,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4400,64500,5200"
st "clk              : IN     std_logic  ;
"
)
)
*7 (CptPort
uid 1529,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1530,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "23000,16625,23750,17375"
)
n "from_ace"
t "std_logic"
m 1
o 20
r 12
tg (CPTG
uid 1531,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1532,0
va (VaSet
)
xt "18900,16500,22000,17500"
st "from_ace"
ju 2
blo "22000,17300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1533,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,10800,64500,11600"
st "from_ace         : OUT    std_logic  ;
"
)
)
*8 (CptPort
uid 1534,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1535,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "23000,6625,23750,7375"
)
n "mp_addr"
t "std_logic_vector"
b "(6 DOWNTO 0)"
m 1
o 14
r 13
tg (CPTG
uid 1536,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1537,0
va (VaSet
)
xt "19100,6500,22000,7500"
st "mp_addr"
ju 2
blo "22000,7300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1538,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,11600,74500,12400"
st "mp_addr          : OUT    std_logic_vector (6 DOWNTO 0) ;
"
)
)
*9 (CptPort
uid 1539,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1540,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,7625,15000,8375"
)
n "mp_addr_1"
t "std_logic_vector"
b "(6 DOWNTO 0)"
o 14
r 5
tg (CPTG
uid 1541,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1542,0
va (VaSet
)
xt "16000,7500,19700,8500"
st "mp_addr_1"
blo "16000,8300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1543,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5200,74500,6000"
st "mp_addr_1        : IN     std_logic_vector (6 DOWNTO 0) ;
"
)
)
*10 (CptPort
uid 1544,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1545,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,10625,15000,11375"
)
n "mp_brdy"
t "std_logic"
o 15
r 6
tg (CPTG
uid 1546,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1547,0
va (VaSet
)
xt "16000,10500,18800,11500"
st "mp_brdy"
blo "16000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1548,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6000,64500,6800"
st "mp_brdy          : IN     std_logic  ;
"
)
)
*11 (CptPort
uid 1549,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1550,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "23000,12625,23750,13375"
)
n "mp_ce_B"
t "std_logic"
m 1
o 16
r 14
tg (CPTG
uid 1551,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1552,0
va (VaSet
)
xt "18900,12500,22000,13500"
st "mp_ce_B"
ju 2
blo "22000,13300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1553,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,12400,64500,13200"
st "mp_ce_B          : OUT    std_logic  ;
"
)
)
*12 (CptPort
uid 1554,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1555,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,8625,15000,9375"
)
n "mp_data_1"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 17
r 7
tg (CPTG
uid 1556,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1557,0
va (VaSet
)
xt "16000,8500,19600,9500"
st "mp_data_1"
blo "16000,9300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1558,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,6800,75000,7600"
st "mp_data_1        : IN     std_logic_vector (15 DOWNTO 0) ;
"
)
)
*13 (CptPort
uid 1559,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1560,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "23000,10625,23750,11375"
)
n "mp_data_dir"
t "std_logic"
m 1
o 20
r 15
tg (CPTG
uid 1561,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1562,0
va (VaSet
)
xt "17100,10500,22000,11500"
st "mp_data_dir"
ju 2
blo "22000,11300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1563,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,13200,64500,14000"
st "mp_data_dir      : OUT    std_logic  ;
"
)
)
*14 (CptPort
uid 1564,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1565,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "23000,18625,23750,19375"
)
n "mp_data_in"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 17
r 8
tg (CPTG
uid 1566,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1567,0
va (VaSet
)
xt "17400,18500,22000,19500"
st "mp_data_in"
ju 2
blo "22000,19300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1568,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7600,75000,8400"
st "mp_data_in       : IN     std_logic_vector (15 DOWNTO 0) ;
"
)
)
*15 (CptPort
uid 1569,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1570,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "23000,8625,23750,9375"
)
n "mp_data_out"
t "std_logic_vector"
b "(15 DOWNTO 0)"
m 1
o 17
r 16
tg (CPTG
uid 1571,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1572,0
va (VaSet
)
xt "17000,8500,22000,9500"
st "mp_data_out"
ju 2
blo "22000,9300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1573,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14000,75000,14800"
st "mp_data_out      : OUT    std_logic_vector (15 DOWNTO 0) ;
"
)
)
*16 (CptPort
uid 1574,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1575,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "23000,13625,23750,14375"
)
n "mp_oe_B"
t "std_logic"
m 1
o 19
r 17
tg (CPTG
uid 1576,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1577,0
va (VaSet
)
xt "18900,13500,22000,14500"
st "mp_oe_B"
ju 2
blo "22000,14300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1578,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,14800,64500,15600"
st "mp_oe_B          : OUT    std_logic  ;
"
)
)
*17 (CptPort
uid 1579,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1580,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "23000,14625,23750,15375"
)
n "mp_we_B"
t "std_logic"
m 1
o 20
r 18
tg (CPTG
uid 1581,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1582,0
va (VaSet
)
xt "18800,14500,22000,15500"
st "mp_we_B"
ju 2
blo "22000,15300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1583,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,15600,63500,16400"
st "mp_we_B          : OUT    std_logic 
"
)
)
*18 (CptPort
uid 1584,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1585,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,21625,15000,22375"
)
n "sw_hw_rst"
t "std_logic"
o 7
r 9
tg (CPTG
uid 1586,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1587,0
va (VaSet
)
xt "16000,21500,19500,22500"
st "sw_hw_rst"
blo "16000,22300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1588,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,8400,64500,9200"
st "sw_hw_rst        : IN     std_logic  ;
"
)
)
*19 (CptPort
uid 1589,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1590,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "14250,11625,15000,12375"
)
n "write"
t "std_logic"
o 1
r 10
tg (CPTG
uid 1591,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1592,0
va (VaSet
)
xt "16000,11500,17600,12500"
st "write"
blo "16000,12300"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 1593,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,9200,64500,10000"
st "write            : IN     std_logic  ;
"
)
)
]
shape (Rectangle
uid 9,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "15000,6000,23000,24000"
)
oxt "15000,6000,23000,22000"
biTextGroup (BiTextGroup
uid 10,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
first (Text
uid 11,0
va (VaSet
font "Arial,8,1"
)
xt "16000,14000,21900,15000"
st "vme_firmware"
blo "16000,14800"
)
second (Text
uid 12,0
va (VaSet
font "Arial,8,1"
)
xt "16000,15000,22000,16000"
st "ace_controller"
blo "16000,15800"
)
)
gi *20 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
uid 14,0
text (MLText
uid 15,0
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "-2000,11000,-2000,11000"
)
header "Generic Declarations"
)
elements [
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
sTC 0
sF 0
)
portVis (PortSigDisplay
sTC 0
sF 0
)
)
*21 (Grouping
uid 16,0
optionalChildren [
*22 (CommentText
uid 18,0
shape (Rectangle
uid 19,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "105000,97000,122000,98000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 20,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "105200,97000,114100,98000"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*23 (CommentText
uid 21,0
shape (Rectangle
uid 22,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "122000,93000,126000,94000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 23,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "122200,93000,124800,94000"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
)
*24 (CommentText
uid 24,0
shape (Rectangle
uid 25,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "105000,95000,122000,96000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 26,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "105200,95000,115200,96000"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
)
*25 (CommentText
uid 27,0
shape (Rectangle
uid 28,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "101000,95000,105000,96000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 29,0
va (VaSet
fg "0,0,32768"
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