--
-- VHDL Architecture vme_managment.clk_sel_reg.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 09:06:05 08/08/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;
USE IEEE.VITAL_Timing.all;

ENTITY clk_sel_reg IS
   PORT( 
      CLK_80        : IN     std_logic;
      data_from_vme : IN     std_logic_VECTOR (31 DOWNTO 0);
      for_clk_sel   : IN     std_logic;
      hw_rst        : IN     std_logic;
      write         : IN     std_logic;
      data_clk_sel  : OUT    std_logic_vector (31 DOWNTO 0)
   );

-- Declarations

END clk_sel_reg ;
ARCHITECTURE rtl OF clk_sel_reg IS
BEGIN
process(clk_80, hw_rst)
begin

If hw_rst = '1' then

	data_clk_sel <= "00000000000000000000000000000001"; -- not zero so boots to Board clk value 100 
	
elsif clk_80'event and clk_80 = '1' then
	
	If (write = '1' and for_clk_sel = '1') then
	
		data_clk_sel <= data_from_vme after 1 ns;
		
	end if;

end if;
end process;
END rtl;

