--
-- VHDL Architecture VME_blockram.delay_data_by1.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 09:14:11 07/14/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY delay_data_by1_mux IS
   PORT( 
      CLK           : IN     std_logic;
      data_out_flip : IN     std_logic_vector (31 DOWNTO 0);
      rst           : IN     std_logic;
      from_bram	    : IN     std_logic;
      from_stat	    : IN     std_logic;
      stat	    : IN     std_logic_vector(31 downto 0);
      data_to_vme   : OUT    std_logic_vector (31 DOWNTO 0)
   );

-- Declarations

END delay_data_by1_mux ;


-- hds interface_end
ARCHITECTURE rtl OF delay_data_by1_mux IS
-- signal temp : std_logic_vector (31 downto 0);
BEGIN


process (clk , rst)
begin
	if rst = '1' then
		data_to_vme 	<= (others => '0');
--		temp 		<= (others => '0');
	elsif clk'event and clk = '1' then

		if from_bram = '1' then
			data_to_vme(0)  <= data_out_flip(31);
			data_to_vme(1)  <= data_out_flip(30);
			data_to_vme(2)  <= data_out_flip(29);
			data_to_vme(3)  <= data_out_flip(28);
			data_to_vme(4)  <= data_out_flip(27);
			data_to_vme(5)  <= data_out_flip(26);
			data_to_vme(6)  <= data_out_flip(25);
			data_to_vme(7)  <= data_out_flip(24);
			data_to_vme(8)  <= data_out_flip(23);
			data_to_vme(9)  <= data_out_flip(22);
			data_to_vme(10) <= data_out_flip(21);
			data_to_vme(11) <= data_out_flip(20);
			data_to_vme(12) <= data_out_flip(19);
			data_to_vme(13) <= data_out_flip(18);
			data_to_vme(14) <= data_out_flip(17);
			data_to_vme(15) <= data_out_flip(16);
			data_to_vme(16) <= data_out_flip(15);
			data_to_vme(17) <= data_out_flip(14);
			data_to_vme(18) <= data_out_flip(13);
			data_to_vme(19) <= data_out_flip(12);
			data_to_vme(20) <= data_out_flip(11);
			data_to_vme(21) <= data_out_flip(10);
			data_to_vme(22) <= data_out_flip(9);
			data_to_vme(23) <= data_out_flip(8);
			data_to_vme(24) <= data_out_flip(7);
			data_to_vme(25) <= data_out_flip(6);
			data_to_vme(26) <= data_out_flip(5);
			data_to_vme(27) <= data_out_flip(4);
			data_to_vme(28) <= data_out_flip(3);
			data_to_vme(29) <= data_out_flip(2);
			data_to_vme(30) <= data_out_flip(1);
			data_to_vme(31) <= data_out_flip(0);
		elsif from_stat = '1' then
			data_to_vme <= stat;
		end if;
		
	end if;		
end process;		
		
END rtl;

