--
-- VHDL Architecture back_end_fpga.FDCE.rtl
--
-- Created:
--          by - st79.UNKNOWN (TE2MOZAMBIQUE)
--          at - 09:21:47 17/08/2004
--
-- using Mentor Graphics HDL Designer(TM) 2003.2 (Build 28)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY FDCE IS
   PORT( 
      C   : IN     std_logic;
      CE  : IN     std_logic;
      CLR : IN     std_logic;
      D   : IN     std_logic;
      Q   : OUT    std_logic
   );

-- Declarations

END FDCE ;

--
ARCHITECTURE rtl OF FDCE IS
   
BEGIN
     process(C, CLR)
     begin
       if (CLR = '1') then
         Q   <= '0';
       elsif (rising_edge(C)) then
         if (CE = '1') then
           Q <= D after 100 ps;
         end if;
       end if;
     end process;
   
END rtl;

