--
-- VHDL Architecture vme_interface.edge_pulse.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 09:16:35 09/26/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1a (Build 22)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY edge_pulse IS
   PORT( 
      clk       : IN     std_logic;
      in_edge   : IN     std_logic;
      rst       : IN     std_logic;
      out_pulse : OUT    std_logic
   );

-- Declarations

END edge_pulse ;


-- hds interface_end
ARCHITECTURE rtl OF edge_pulse IS
signal a : std_logic;
BEGIN
process ( clk , rst)
begin
  if rst = '1' then
  	out_pulse <= '0';
	a <= '0';
  elsif clk'event and clk = '1' then
	a <= in_edge;

   	if (a /= in_edge) then
		out_pulse <= in_edge;
	else
		out_pulse <= '0';
    end if;
  end if;
end process;
END rtl;

