--
-- VHDL Architecture back_end_fpga.FDC.rtl
--
-- Created:
--          by - st79.UNKNOWN (TE2MOZAMBIQUE)
--          at - 09:45:56 17/08/2004
--
-- using Mentor Graphics HDL Designer(TM) 2003.2 (Build 28)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY FDC IS
   PORT( 
      C   : IN     std_logic;
      CLR : IN     std_logic;
      D   : IN     std_logic;
      Q   : OUT    std_logic
   );

-- Declarations

END FDC ;

--
ARCHITECTURE rtl OF FDC IS
BEGIN
     process(CLR, C)
     begin
   
       if (CLR = '1') then
         Q <= '0';
       elsif (rising_edge(C)) then
         Q <= D after 100 ps;
       end if;
   end process;
   
END rtl;

