--
-- VHDL Architecture VME_blockram.ff.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 09:20:18 12/19/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY be_data_dly IS
   PORT( 
    	CLK     		: IN     std_logic;
         data_from_be_int 	: IN     std_logic_vector(63 downto 0);
         rst          		: IN     std_logic;
         data_from_be 		: OUT    std_logic_vector(63 downto 0)
   );

-- Declarations

END be_data_dly ;


-- hds interface_end
ARCHITECTURE rtl OF be_data_dly IS
BEGIN
process (clk ,rst)
begin
	if rst = '1' then
	 	data_from_be <= (others => '0');
	elsif clk'event and clk = '1' then 
		data_from_be  	<= data_from_be_int;
     
	end if;
end process;
END rtl;

