--
-- VHDL Architecture VME_blockram.mux_1to9.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 09:46:54 02/21/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY mux_1to9_and_back IS
   PORT( 
      clk           : IN     std_logic;
      command_to_FE : IN     std_logic;
      commandin_a   : IN     std_logic;
      commandin_b   : IN     std_logic;
      commandin_c   : IN     std_logic;
      commandin_d   : IN     std_logic;
      commandin_e   : IN     std_logic;
      commandin_f   : IN     std_logic;
      commandin_g   : IN     std_logic;
      commandin_h   : IN     std_logic;
      commandin_i   : IN     std_logic;
      commandin_j   : IN     std_logic;
      en_mux_in     : IN     std_logic;
      rst           : IN     std_logic;
      selt          : IN     std_logic_vector (4 DOWNTO 0);
      commandout_a  : OUT    std_logic;
      commandout_b  : OUT    std_logic;
      commandout_c  : OUT    std_logic;
      commandout_d  : OUT    std_logic;
      commandout_e  : OUT    std_logic;
      commandout_f  : OUT    std_logic;
      commandout_g  : OUT    std_logic;
      commandout_h  : OUT    std_logic;
      commandout_i  : OUT    std_logic;
      commandout_j  : OUT    std_logic;
      data_from_FE  : OUT    std_logic
   );

-- Declarations

END mux_1to9_and_back ;
ARCHITECTURE rtl OF mux_1to9_and_back IS
BEGIN
process (clk,rst)
begin
if rst = '1' then
	Commandout_a <= '0';
	Commandout_b <= '0';
	Commandout_c <= '0';
	Commandout_d <= '0';
	Commandout_e <= '0';
	Commandout_f <= '0';
	Commandout_g <= '0';
	Commandout_h <= '0';
	Commandout_i <= '0';
	Commandout_j <= '0';

elsif clk'event and clk = '1' then

	if en_mux_in = '1' then

		case selt is 


			when "00001" =>
				Commandout_a <= command_to_FE;
				Commandout_b <= '0';
				Commandout_c <= '0';
				Commandout_d <= '0';
				Commandout_e <= '0';
				Commandout_f <= '0';
				Commandout_g <= '0';
				Commandout_h <= '0';
				Commandout_i <= '0';
				Commandout_j <= '0';
				data_from_FE <= commandin_a;

			when "00010" => 
				Commandout_a <= '0';
				Commandout_b <= command_to_FE;
				Commandout_c <= '0';
				Commandout_d <= '0';
				Commandout_e <= '0';
				Commandout_f <= '0';
				Commandout_g <= '0';
				Commandout_h <= '0';
				Commandout_i <= '0';
				Commandout_j <= '0';
				data_from_FE <= commandin_b;

			when "00011" => 
				Commandout_a <= '0';
				Commandout_b <= '0';
				Commandout_c <= command_to_FE;
				Commandout_d <= '0';
				Commandout_e <= '0';
				Commandout_f <= '0';
				Commandout_g <= '0';
				Commandout_h <= '0';
				Commandout_i <= '0';
				Commandout_j <= '0';
				data_from_FE <= commandin_c;

			when "00100" => 
				Commandout_a <= '0';
				Commandout_b <= '0';
				Commandout_c <= '0';
				Commandout_d <= command_to_FE;
				Commandout_e <= '0';
				Commandout_f <= '0';
				Commandout_g <= '0';
				Commandout_h <= '0';
				Commandout_i <= '0';
				Commandout_j <= '0';
				data_from_FE <= commandin_d;

			when "00101" => 
				Commandout_a <= '0';
				Commandout_b <= '0';
				Commandout_c <= '0';
				Commandout_d <= '0';
				Commandout_e <= command_to_FE;
				Commandout_f <= '0';
				Commandout_g <= '0';
				Commandout_h <= '0';
				Commandout_i <= '0';
				Commandout_j <= '0';
				data_from_FE <= commandin_e;

			when "00110" => 
				Commandout_a <= '0';
				Commandout_b <= '0';
				Commandout_c <= '0';
				Commandout_d <= '0';
				Commandout_e <= '0';
				Commandout_f <= command_to_FE;
				Commandout_g <= '0';
				Commandout_h <= '0';
				Commandout_i <= '0';
				Commandout_j <= '0';
				data_from_FE <= commandin_f;

			when "00111" => 
				Commandout_a <= '0';
				Commandout_b <= '0';
				Commandout_c <= '0';
				Commandout_d <= '0';
				Commandout_e <= '0';
				Commandout_f <= '0';
				Commandout_g <= command_to_FE;
				Commandout_h <= '0';
				Commandout_i <= '0';
				Commandout_j <= '0';
				data_from_FE <= commandin_g;

			when "01000" => 
				Commandout_a <= '0';
				Commandout_b <= '0';
				Commandout_c <= '0';
				Commandout_d <= '0';
				Commandout_e <= '0';
				Commandout_f <= '0';
				Commandout_g <= '0';
				Commandout_h <= command_to_FE;
				Commandout_i <= '0';
				Commandout_j <= '0';
				data_from_FE <= commandin_h;

			when "01001" => 
				Commandout_a <= '0';
				Commandout_b <= '0';
				Commandout_c <= '0';
				Commandout_d <= '0';
				Commandout_e <= '0';
				Commandout_f <= '0';
				Commandout_g <= '0';
				Commandout_h <= '0';
				Commandout_i <= command_to_FE;
				Commandout_j <= '0';
				data_from_FE <= commandin_i;

			when "01010" => 
				Commandout_a <= '0';
				Commandout_b <= '0';
				Commandout_c <= '0';
				Commandout_d <= '0';
				Commandout_e <= '0';
				Commandout_f <= '0';
				Commandout_g <= '0';
				Commandout_h <= '0';
				Commandout_i <= '0';
				Commandout_j <= command_to_FE;
				data_from_FE <= commandin_j;


			when others => 
				Commandout_a <= '0';
				Commandout_b <= '0';
				Commandout_c <= '0';
				Commandout_d <= '0';
				Commandout_e <= '0';
				Commandout_f <= '0';
				Commandout_g <= '0';
				Commandout_h <= '0';
				Commandout_i <= '0';
				data_from_FE <= '0';

		  end case;
		
		
		
		else  
		  
	  		Commandout_a <= '0';
	  		Commandout_b <= '0';
	  		Commandout_c <= '0';
	  		Commandout_d <= '0';
	  		Commandout_e <= '0';
	  		Commandout_f <= '0';
	  		Commandout_g <= '0';
	  		Commandout_h <= '0';
	  		Commandout_i <= '0';
			data_from_FE <= '0';
		  
		  
		  
		  
		  
		  
		end if;	  
 	end if;
end process;
END rtl;

