--
-- VHDL Architecture VME_serial.counter_15bit.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 15:50:58 08/08/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY counter_15bit IS
   PORT( 
      clk   : IN     std_logic;
      rst   : IN     std_logic;
      count : OUT    std_logic_vector (31 DOWNTO 0)
   );

-- Declarations

END counter_15bit ;


-- hds interface_end
ARCHITECTURE rtl OF counter_15bit IS
BEGIN
process(clk,rst)
variable v_count : unsigned(31 downto 0);
begin

If rst = '1' then
	
 v_count := (others => '0');
 
 elsif clk'event and clk = '1' then
 	v_count := v_count + 1;
 end if;
 

count <= conv_std_logic_vector(v_count,32);


end process;
END rtl;

