--
-- VHDL Architecture cmm.ff.symbol
--
-- Created:
--          by - ipb28.UNKNOWN (TE2WILLENSTAD)
--          at - 08:49:10 09/10/01
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.3 (Build 11)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;


ENTITY i2c_ff IS
   GENERIC( 
      q_rst : std_logic := '0'
   );
   PORT( 
      d   : IN     std_logic;
      clk : IN     std_logic;
      rst : IN     std_logic;
      q   : OUT    std_logic
   );

-- Declarations

END i2c_ff ;


-- hds interface_end
--------------------------------------------------------------------------------
ARCHITECTURE rtl OF i2c_ff IS
--------------------------------------------------------------------------------
-- flip-flop, async reset, clocked on rising edge.
--

--------------------------------------------------------------------------------
BEGIN


  regproc: process (rst, clk, d)
  begin
    if (rst = '1') then
      q <= q_rst;
    elsif (clk'event and clk = '1') then
      q <= d;

      -- functional timing stuff:
      -- pragma synthesis_off
      if (d'stable(1 ns) = false) then
        q <= d'last_value;
      end if;
      -- pragma synthesis_on

    end if;
  end process;
END rtl;

