-- hds interface_start
-- Coregen VHDL wrapper file modified by HDL Designer

--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2002 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- You must compile the wrapper file p_s_shiftreg32.vhd when simulating
-- the core, p_s_shiftreg32. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "Coregen Users Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Express, Exemplar and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY p_s_shiftreg32 IS
	port (
	CLK: IN std_logic;
	SDOUT: OUT std_logic;
	P_LOAD: IN std_logic;
	D: IN std_logic_VECTOR(31 downto 0));
END p_s_shiftreg32;


-- hds interface_end


-- pragma synthesis_off
ARCHITECTURE p_s_shiftreg32_a OF p_s_shiftreg32 IS

component wrapped_p_s_shiftreg32
	port (
	CLK: IN std_logic;
	SDOUT: OUT std_logic;
	P_LOAD: IN std_logic;
	D: IN std_logic_VECTOR(31 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_p_s_shiftreg32 use entity XilinxCoreLib.C_SHIFT_FD_V5_0(behavioral)
		generic map(
			c_has_aset => 0,
			c_has_d => 1,
			c_sync_priority => 1,
			c_has_sclr => 0,
			c_fill_data => 0,
			c_width => 32,
			c_enable_rlocs => 1,
			c_ainit_val => "00000000000000000000000000000000",
			c_has_ce => 0,
			c_has_aclr => 0,
			c_sync_enable => 0,
			c_has_ainit => 0,
			c_has_sdout => 1,
			c_sinit_val => "00000000000000000000000000000000",
			c_has_sset => 0,
			c_has_sinit => 0,
			c_has_q => 0,
			c_shift_type => 1,
			c_has_sdin => 0,
			c_has_lsb_2_msb => 0);
BEGIN

U0 : wrapped_p_s_shiftreg32
		port map (
			CLK => CLK,
			SDOUT => SDOUT,
			P_LOAD => P_LOAD,
			D => D);
END p_s_shiftreg32_a;

-- pragma synthesis_on



