--
-- VHDL Architecture VME_blockram.ff.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 09:20:18 12/19/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY edd_ff IS
   PORT( 
      CLK          : IN     std_logic;
      en_write_out : IN     std_logic;
      rst          : IN     std_logic;
      write_out    : OUT    std_logic
   );

-- Declarations

END edd_ff ;


-- hds interface_end
ARCHITECTURE rtl OF edd_ff IS
BEGIN
process (clk ,rst)
begin
	if rst = '1' then
	 	write_out <= '0' after 1 ns;
	elsif clk'event and clk = '1' then 
		write_out <= en_write_out after 1 ns;
	end if;
end process;
END rtl;

