--
-- VHDL Architecture VME_blockram.delay24.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 16:01:46 04/07/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY delay_24 IS
   PORT( 
      clk        : IN     std_logic;
      en_mux_in  : IN     std_logic;
      rst        : IN     std_logic;
      en_mux_out : OUT    std_logic
   );

-- Declarations

END delay_24 ;


-- hds interface_end
ARCHITECTURE rtl OF delay_24 IS
signal reg : std_logic_vector(24 downto 0);
BEGIN
process(clk ,rst)
BEGIN

if rst = '1' then
	en_mux_out 	<= '0';
	reg 		<= (others => '0');	
	
elsif clk'event and clk = '1' then
	reg 		<= (reg(23 downto 0) & en_mux_in);
	en_mux_out 	<= reg(24);

end if;
end process;
END rtl;

