--
-- VHDL Architecture vme_interface.delay_2.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 13:42:00 10/08/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1a (Build 22)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY delay_2 IS
   PORT( 
      clk     : IN     std_logic;
      rst     : IN     std_logic;
      sig_in  : IN     std_logic;
      sig_out : OUT    std_logic
   );

-- Declarations

END delay_2 ;


-- hds interface_end
ARCHITECTURE rtl OF delay_2 IS
signal a,b : std_logic;
BEGIN
process (clk,rst)
begin
   if rst = '1' then
	   	a <= '0';
   		b <= '0';
		sig_out <= '0';
		

   elsif clk 'event and clk = '1' then
   		a <= sig_in;
		b <= a;
		
		sig_out <= b;
   		
   end if;
end process;
END rtl;

