--
-- VHDL Architecture fed.counter.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 09:11:59 01/09/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY counter IS
   PORT( 
      count : OUT    std_logic_vector (27 DOWNTO 0);
      clk   : IN     std_logic;
      rst   : IN     std_logic
   );

-- Declarations

END counter ;


-- hds interface_end
ARCHITECTURE rtl OF counter IS
BEGIN
process(clk,rst)
variable v_count : integer;
begin
	if rst = '1' then
		count <= (others => '1');
		v_count := 0;
	elsif clk'event and clk = '1' then
	 	v_count := v_count + 1;
		count <= conv_std_logic_vector(v_count,28);
	end if;
end process;
END rtl;

