--
-- VHDL Architecture vme_slink.delay_msb_by1.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 11:45:10 07/23/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY delay_msb_by1 IS
   PORT( 
      clk                  : IN     std_logic;
      data_from_be_msb_in  : IN     std_logic_VECTOR (31 DOWNTO 0);
      rst                  : IN     std_logic;
      data_from_be_msb_out : OUT    std_logic_VECTOR (31 DOWNTO 0)
   );

-- Declarations

END delay_msb_by1 ;


-- hds interface_end
ARCHITECTURE rtl OF delay_msb_by1 IS
--signal a, b : std_logic_vector(31 downto 0);
BEGIN

process(clk,rst)
begin

	if rst = '1' then
		data_from_be_msb_out <= (others => '0');
		
		
	elsif clk'event and clk = '1' then
		 
		data_from_be_msb_out <= data_from_be_msb_in;
		
		
		

end if;

end process;
END rtl;

