--
-- VHDL Architecture vme_slink.run_data_reg.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 16:22:19 06/23/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY run_data_reg IS
   PORT( 
      clear_run_data_reg : IN     std_logic;
      clk                : IN     std_logic;
      data               : IN     std_logic_VECTOR (31 DOWNTO 0);
      match_1            : IN     std_logic;
      rst                : IN     std_logic;
      write		 : IN  	  std_logic;
      run_data           : OUT    std_logic_vector (31 DOWNTO 0);
      last               : IN     std_logic					-- 1 if last part of an event else 0
   );

-- Declarations

END run_data_reg ;


-- hds interface_end
ARCHITECTURE rtl OF run_data_reg IS
BEGIN
process(clk,rst)
begin
if rst = '1' then

	run_data <= "00000000000000000000000000000000";

elsif clk'event and clk = '1' then

	if ( match_1 = '1' and write = '1') then
		run_data <= data;
	elsif clear_run_data_reg = '1' then
		run_data <= ("000000000000000000000000000000" & last & '1');
	end if;
	
end if;

end process;

END rtl;

