--
-- VHDL Architecture fed.pulse_96.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 14:29:12 05/06/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY pulse_96 IS
   PORT( 
      clk           : IN     std_logic;
      rst           : IN     std_logic;
      commandout_i  : IN     std_logic;
      frame_sync_in : OUT    std_logic;
      read_sync_in  : OUT    std_logic
   );

-- Declarations

END pulse_96 ;


-- hds interface_end
ARCHITECTURE rtl OF pulse_96 IS
BEGIN
process(clk,rst)
variable count : unsigned(8 downto 0);
begin
if rst = '1' then
	count := "000000000";
	frame_sync_in <= '0' ;
	read_sync_in <= '0';
elsif clk'event and clk = '1' then 



	if commandout_i = '1' then
		count := "111111111" ;
	end if;
	
	if count > 0 then	
		count := count - 1;
	end if;
	
	if (count = 97) then
		frame_sync_in <= '1';
	else
		frame_sync_in <= '0';
		
	end if;
	
	if (count = 1) then
		read_sync_in <= '1';
	else
		read_sync_in <= '0';
	end if;
	
			

end if;
end process;	
END rtl;

