--
-- VHDL Architecture VME_blockram.length_reg.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 10:43:30 11/15/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY write_length_reg IS
   PORT( 
      CLK           : IN     std_logic;
      data          : IN     std_logic_vector (31 DOWNTO 0);
      en_length_reg : IN     std_logic;
      rst           : IN     std_logic;
      write_length  : OUT    std_logic_VECTOR (31 DOWNTO 0)
   );

-- Declarations

END write_length_reg ;


-- hds interface_end
ARCHITECTURE rtl OF write_length_reg IS
BEGIN
process (clk,rst)
begin
	if rst = '1' then
 		write_length <= (others => '0');
	elsif clk'event and clk = '1' then
		If en_length_reg = '1' then
	    		write_length<= data;	
			    	
		end if;
	end if;
end process;
END rtl;

