--
-- VHDL Architecture vme_slink.make_twice_the_size.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 14:34:46 09/03/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY make_twice_the_size IS
   PORT( 
      clear_run_data_reg      : IN     std_logic;
      clk                     : IN     std_logic;
      rst                     : IN     std_logic;
      clear_run_data_reg_wide : OUT    std_logic
   );

-- Declarations

END make_twice_the_size ;


-- hds interface_end
ARCHITECTURE rtl OF make_twice_the_size IS
signal a : std_logic;
BEGIN
process (clk,rst)
begin
if rst = '1' then

	clear_run_data_reg_wide <= '0';
	a 			<= '0';
	
elsif clk'event and clk = '1' then
	a <= clear_run_data_reg;
	If ((a = '1')  or (clear_run_data_reg = '1')) then
	 
		clear_run_data_reg_wide <= '1';
	else
		clear_run_data_reg_wide <= '0';
	end if;
end if;
end process;
END rtl;

