--
-- VHDL Architecture VME_blockram.address_decoder.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 11:35:07 10/31/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY address_decoder_22 IS
   
   PORT( 
      address_decode : IN     std_logic_vector (4 DOWNTO 0);
      clk            : IN     std_logic;
      data_latch     : IN     std_logic;
      rst            : IN     std_logic;
      en_bram        : OUT    std_logic
   );

-- Declarations

END address_decoder_22 ;


-- hds interface_end
ARCHITECTURE rtl OF address_decoder_22 IS
BEGIN
process(clk,rst)

begin
	if rst = '1' then
		en_bram <= '0';
		
	elsif clk'event and clk = '1' then

		if data_latch = '1' then		-- data ready signal
			case address_decode is
				when "00000" => 
							en_bram <= '1';											
				when others =>
							en_bram <= '0';
				end case;
		else
			en_bram <= '0';
			
	 	end if;
	end if;
end process;
END rtl;

