--
-- VHDL Architecture VME_blockram.from_serial_lineup.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 14:13:03 07/02/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY from_serial_lineup IS
   PORT( 
      CLK              : IN     std_logic;
      en_brama         : IN     std_logic;
      rst              : IN     std_logic;
      from_serial_bram : OUT    STD_ULOGIC
   );

-- Declarations

END from_serial_lineup ;


-- hds interface_end
ARCHITECTURE rtl OF from_serial_lineup IS
   signal temp : std_logic;
BEGIN

process ( clk,rst)
begin

	If rst = '1' then
		from_serial_bram <= '0';
		temp <= '0';
--		temp1 <= '0';
--		temp2 <= '0';
		
	elsif clk'event and clk = '1' then
		temp <= en_brama;
--		temp1 <= temp;
--		temp2 <= temp1;
		from_serial_bram <= temp;
		
	end if;

end process;
END rtl;

