--
-- VHDL Architecture vme_interface.led_flash_once.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 08:54:34 03/10/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY led_flash_once IS
   PORT( 
      clk       : IN     std_logic;
      rst       : IN     std_logic;
      in_pulse  : IN     std_logic;
      out_pulse : OUT    std_logic
   );

-- Declarations

END led_flash_once ;


-- hds interface_end
ARCHITECTURE rtl OF led_flash_once IS
BEGIN
process(clk,rst)
variable count : integer;
begin
	if rst = '1' then
		count 		:= 0;
		out_pulse 	<= '0';
	elsif clk'event and clk = '1' then

		If in_pulse = '1' then
			count := 20000000;			-- 24 bits for synth
	   	end if;

 	    if count /= 0 then
			count := count - 1;
			out_pulse <= '1';
		else
			out_pulse <= '0';
		end if;
	end if;
end process;
END rtl;

