--
-- VHDL Architecture vme_firmware.ack_gen.rtl
--
-- Created:
--          by - st79.UNKNOWN (TE2BELIZE)
--          at - 12:03:02 01/06/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY tst_eprom_ack IS
   PORT( 
      id_eprom_sda : INOUT  std_logic
   );

-- Declarations

END tst_eprom_ack ;
ARCHITECTURE rtl OF tst_eprom_ack IS
BEGIN
-- this is the acknowlege generator

process
begin
	id_eprom_sda <= 'Z';
	wait for 133.2 us;  -- 1st dir cnage
	id_eprom_sda <= '0';   
	wait for 12 us;   
	id_eprom_sda <= 'Z';
	wait for 104 us;  -- 2nd dir cnage
	id_eprom_sda <= '0';   
	wait for 12 us;
	id_eprom_sda <= 'Z';
	wait for 103 us;  -- 3rd dir cnage
	id_eprom_sda <= '0';   
	wait for 12 us;
	id_eprom_sda <= 'Z';
	wait for 154 us;  -- 4th dir cnage
	id_eprom_sda <= '0';   
	wait for 12 us;
	id_eprom_sda <= 'Z';
	wait for 104 us;  -- 5th dir cnage
	id_eprom_sda <= '0';   
	wait for 12 us;
	id_eprom_sda <= 'Z';
	wait for 155 us;  -- 6th dir cnage
	id_eprom_sda <= '0';   
	wait for 11 us;
	id_eprom_sda <= 'Z';
	wait for 2 us;  	  -- 2 data bits
	id_eprom_sda <= '1';   
	wait for 25.625 us;  	  -- 2 data bits
	id_eprom_sda <= '0';   
	wait for 25.625 us;  	  -- 2 data bits
	id_eprom_sda <= '1';   
	wait for 25.625 us;	     -- 2 data bits
	id_eprom_sda <= '0';
	wait for 25.625 us;
	id_eprom_sda <= 'Z';
	wait;
	end process;
END rtl;

