--
-- VHDL Architecture vme_firmware.tst_lm82_ack.lm82_rtl
--
-- Created:
--          by - st79.UNKNOWN (TE2MALDIVES)
--          at - 15:33:38 02/10/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY tst_lm82_ack IS
   PORT( 
      lm82_sda : INOUT  std_logic
   );

-- Declarations

END tst_lm82_ack ;
ARCHITECTURE lm82_rtl OF tst_lm82_ack IS
BEGIN
process
begin
	lm82_sda <= 'Z';
	wait for 133.2 us;  -- 1st dir cnage
	lm82_sda <= '0';   
	wait for 12 us;   
	lm82_sda <= 'Z';
	wait for 104 us;  -- 2nd dir cnage
	lm82_sda <= '0';   
	wait for 12 us;
	lm82_sda <= 'Z';
	wait for 103 us;  -- 3rd dir cnage
	lm82_sda <= '0';   
	wait for 12 us;
	lm82_sda <= 'Z';
	wait for 154 us;  -- 4th dir cnage
	lm82_sda <= '0';   
	wait for 12 us;
	lm82_sda <= 'Z';
	wait for 104 us;  -- 5th dir cnage
	lm82_sda <= '0';   
	wait for 12 us;
	lm82_sda <= 'Z';
	wait for 155 us;  -- 6th dir cnage
	lm82_sda <= '0';   
	wait for 11 us;
	lm82_sda <= 'Z';
	wait for 2 us;  	  -- 2 data bits
	lm82_sda <= '1';   
	wait for 25.625 us;  	  -- 2 data bits
	lm82_sda <= '0';   
	wait for 25.625 us;  	  -- 2 data bits
	lm82_sda <= '1';   
	wait for 25.625 us;	     -- 2 data bits
	lm82_sda <= '0';
	wait for 25.625 us;
	lm82_sda <= 'Z';
	wait;
	end process;

END lm82_rtl;

