--
-- VHDL Architecture vme_interface.dtack_manager.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 11:55:34 06/11/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
-- synopsys translate_off
LIBRARY UNISIM;
USE UNISIM.all;
-- synopsys translate_on

ENTITY dtack_manager IS
   PORT( 
      n_dtack        : IN     std_logic;
      rst            : IN     std_logic;
      dtack_dir_ctrl : OUT    std_logic;
      dtack_out      : OUT    std_logic
   );

-- Declarations

END dtack_manager ;
   ARCHITECTURE rtl OF dtack_manager IS
   BEGIN
   with n_dtack select
   	dtack_out <=	'Z' when '1',
   			'0' when '0',
   			'Z' when others;
   			
   
   with n_dtack select
   	dtack_dir_ctrl <= 	'0' when '1',
   				'1' when '0',
   				'0' when others;
   END rtl;

