--
-- VHDL Architecture VME_blockram.mux_32.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 09:36:15 12/10/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY mux_32 IS
   PORT( 
      CLK                        : IN     std_logic;
      data_to_serialise_blockram : IN     std_logic_vector (31 DOWNTO 0);
      lng_rd_cmnd_lsb            : IN     std_logic_vector (31 DOWNTO 0);
      lng_rd_cmnd_msb            : IN     std_logic_vector (31 DOWNTO 0);
      read_command               : IN     std_logic_vector (31 DOWNTO 0);
      rst                        : IN     std_logic;
      sel_mux                    : IN     std_logic_vector (1 DOWNTO 0);
      data_to_serialise          : OUT    std_logic_vector (31 DOWNTO 0)
   );

-- Declarations

END mux_32 ;
ARCHITECTURE rtl OF mux_32 IS
BEGIN
with sel_mux select 
	data_to_serialise <= read_command when "01",	 -- selects read command
						 lng_rd_cmnd_msb when "10",   -- selects read long command msb 1st
						 lng_rd_cmnd_lsb when "11",   -- selects read long command 1sb 2nd
	data_to_serialise_blockram  when others;
END rtl;

