--
-- VHDL Architecture vme_firmware.SR_16bits.rtl
--
-- Created:
--          by - st79.UNKNOWN (TE2BELIZE)
--          at - 14:32:40 12/05/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY SR_16bits IS
   PORT( 
      clk            : IN     std_logic;
      hw_rst         : IN     std_logic;
      sw_reset       : IN     std_logic;
      delayed_sw_rst : OUT    std_logic
   );

-- Declarations

END SR_16bits ;
ARCHITECTURE rtl OF SR_16bits IS

signal SR_count : unsigned(15 downto 0);

BEGIN
-- this is a 16 bit shift register

process(hw_rst, clk)
begin
   if hw_rst = '1' then
      delayed_sw_rst <= '0';
      SR_count <= (others => '0');
   elsif clk'event and clk = '1' then
    	SR_count <= SR_count(14 downto 0) & sw_reset after 1 ns;
   	delayed_sw_rst <= SR_count(15) after 1 ns;
   end if;
end process;
END rtl;

