--
-- VHDL Architecture back_end_fpga.INV.rtl
--
-- Created:
--          by - st79.UNKNOWN (TE2MOZAMBIQUE)
--          at - 09:18:28 17/08/2004
--
-- using Mentor Graphics HDL Designer(TM) 2003.2 (Build 28)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY INV IS
   PORT( 
      I : IN     std_logic;
      O : OUT    std_logic
   );

-- Declarations

END INV ;

--
ARCHITECTURE rtl OF INV IS
BEGIN
   O <= NOT I after 100 ps;
END rtl;

