--
-- VHDL Architecture vme_slink.length_counter.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 14:15:33 06/26/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY length_counter IS
   PORT( 
      clk   : IN     std_logic;
      en    : IN     std_logic;
      rst   : IN     std_logic;
      count : OUT    std_logic_vector (31 DOWNTO 0)
   );

-- Declarations

END length_counter ;

ARCHITECTURE rtl OF length_counter IS

BEGIN

process(clk,rst)

variable v_count : unsigned(30 downto 0);

begin
	if rst = '1' then
-- 		count 	<= (others => '0');
		v_count := (others => '0');
	elsif clk'event and clk = '1' then

		IF en = '1' then
			v_count := v_count + 1;
		end if;
		count <= (conv_std_logic_vector(v_count,31) & '0');
   	end if;
end process;
END rtl;

