--
-- VHDL Architecture vme_slink.address_decoder.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 11:15:08 06/23/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY address_decoder IS
   PORT( 
      address_from_vme : IN     std_logic_vector (15 DOWNTO 0);
      clk              : IN     std_logic;
      rst              : IN     std_logic;
      data_latch       : IN 	std_logic;
      en_a             : OUT    std_logic
   );

-- Declarations

END address_decoder ;


-- hds interface_end
ARCHITECTURE rtl OF address_decoder IS
BEGIN
process(clk,rst)

begin
	if rst = '1' then
		en_a <= '0';
		
	elsif clk'event and clk = '1' then

		if data_latch = '1' then
			If address_from_vme(15) = '1' then
				en_a <= '1';											
			else
				en_a <= '0';
			end if;
		else
			en_a <= '0';
			
	 	end if;
	end if;
end process;
END rtl;

