--
-- VHDL Architecture vme_managment.stat_reg.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 09:13:06 08/08/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;
USE IEEE.VITAL_Timing.all;

ENTITY status_reg IS
   PORT( 
      CLK_80        : IN     std_logic;
      data_from_vme : IN     std_logic_VECTOR (31 DOWNTO 0);
      for_stat_reg  : IN     std_logic;
      rst           : IN     std_logic;
      write         : IN     std_logic;
      data_stat_reg : OUT    std_logic_vector (31 DOWNTO 0)
   );

-- Declarations

END status_reg ;
ARCHITECTURE rtl OF status_reg IS
BEGIN
process(clk_80,rst)
begin

If rst = '1' then

	data_stat_reg <= ( others => '0');
	
elsif clk_80'event and clk_80 = '1' then
	
	If (write = '1' and for_stat_reg = '1') then
	
		data_stat_reg <= data_from_vme after 1 ns;
		
	end if;
end if;

end process;
END rtl;

