--
-- VHDL Architecture vme_interface.tri_driver.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 13:58:46 09/05/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1a (Build 22)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY tri_driver IS
   GENERIC( 
      width : integer := 32
   );
   PORT( 
      clk         : IN     std_logic;
      data_output : IN     std_logic_VECTOR (width - 1 DOWNTO 0);
      rst         : IN     std_logic;
      write_out   : IN     std_logic;
      path_in_a   : OUT    std_logic_vector (width - 1 DOWNTO 0);
      data_a      : INOUT  std_logic_vector (width - 1 DOWNTO 0)
   );

-- Declarations

END tri_driver ;


-- hds interface_end
ARCHITECTURE rtl OF tri_driver IS
BEGIN
process (clk , rst)
begin
	if rst = '1' then
		data_a <= ( others => 'Z');
	elsif
		clk'event and clk = '1' then
		if write_out = '1' then
			data_a <= data_output;
		else
			path_in_a <= data_a;
			data_a <= (others => 'Z');
		end if;
  end if;
end process;

-- needed to tack a clk longer so make clocked


--with write_out select

--data_a <=  data_output when '1',
--			(others => 'Z') when others;
--path_in_a <= data_a;

END rtl;

