--
-- VHDL Architecture VME_blockram.stat_reg.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 11:38:17 09/05/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY stat_reg IS
   PORT( 
      CLK           : IN     std_logic;
      data          : IN     std_logic_vector (31 DOWNTO 0);
      en_stat_reg   : IN     std_logic;
      write	    : IN     std_logic;
      rst           : IN     std_logic;
      set_stat_busy : IN     std_logic;
      stat          : OUT    std_logic_vector (31 DOWNTO 0)
   );

-- Declarations

END stat_reg ;


-- hds interface_end
ARCHITECTURE rtl OF stat_reg IS
BEGIN
process (clk, rst )
begin
if rst = '1' then
	stat <= (others => '1');
elsif clk'event and clk = '1' then
	
	if ((en_stat_reg = '1') and (write = '1')) then
	
			stat <= data;
			
	elsif set_stat_busy = '1' then
			stat <= (others => '0');
	else 
			stat <= (others => '1');
		
	end if;	

end if;
end process;
END rtl;

