--
-- VHDL Architecture vme_firmware.mk_4_long.rtl
--
-- Created:
--          by - st79.UNKNOWN (TE2MALDIVES)
--          at - 15:03:40 09/11/2004
--
-- using Mentor Graphics HDL Designer(TM) 2003.2 (Build 28)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY mk_4_long IS
   PORT( 
      CLK : IN     std_logic;
      D   : IN     std_logic;
      RST : IN     std_logic;
      Q   : OUT    std_logic
   );

-- Declarations

END mk_4_long ;

--
ARCHITECTURE rtl OF mk_4_long IS
   signal a,b,c,e : std_logic;
BEGIN
   process (CLK, RST)
      begin
      if RST = '1' then
	   	     a <= '0';
   		      b <= '0';
	   	     c <= '0';
 		      e <= '0';
		      Q <= '0';
      elsif CLK 'event and CLK = '1' then
   		      a <= D;
		      b <= a;
		      c <= b;
		      e <= c;
		      Q <=  a OR b OR c OR e after 1 ns;
      end if;
      end process;
END rtl;

