--
-- VHDL Architecture VME_blockram.read_command_reg.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 09:37:07 11/29/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY read_command_reg IS
   PORT( 
      CLK          : IN     std_logic;
      data         : IN     std_logic_vector (31 DOWNTO 0);
      en_read_reg  : IN     std_logic;
      rst          : IN     std_logic;
      read_command : OUT    std_logic_vector (31 DOWNTO 0)
   );

-- Declarations

END read_command_reg ;
ARCHITECTURE rtl OF read_command_reg IS
BEGIN

process (clk,rst)
begin
	if rst = '1' then
 		read_command <= (others => '0');
	elsif clk'event and clk = '1' then
		If en_read_reg = '1' then
	    	read_command(0) <= data(31);	
	    	read_command(1) <= data(30);	
	    	read_command(2) <= data(29);	
	    	read_command(3) <= data(28);	
	    	read_command(4) <= data(27);	
	    	read_command(5) <= data(26);
	    	read_command(6) <= data(25);
	    	read_command(7) <= data(24);	
	    	read_command(8) <= data(23);	
	    	read_command(9) <= data(22);
	    	read_command(10) <= data(21);
	    	read_command(11) <= data(20);	
	    	read_command(12) <= data(19);	
	    	read_command(13) <= data(18);	
	    	read_command(14) <= data(17);	
	    	read_command(15) <= data(16);	
	    	read_command(16) <= data(15);	
	    	read_command(17) <= data(14);	
	    	read_command(18) <= data(13);	
	    	read_command(19) <= data(12);	    	
	    	read_command(20) <= data(11);
	    	read_command(21) <= data(10);	
	    	read_command(22) <= data(9);	
	    	read_command(23) <= data(8);	
	    	read_command(24) <= data(7);	
	    	read_command(25) <= data(6);	
	    	read_command(26) <= data(5);	
	    	read_command(27) <= data(4);	
	    	read_command(28) <= data(3);
	    	read_command(29) <= data(2);
	    	read_command(30) <= data(1);	
	    	read_command(31) <= data(0);	
	    
		end if;
	end if;
end process;
END rtl;


