--
-- VHDL Architecture vme_firmware.bus_error.rtl
--
-- Created:
--          by - st79.UNKNOWN (TE2MALDIVES)
--          at - 11:32:26 22/09/2004
--
-- using Mentor Graphics HDL Designer(TM) 2003.2 (Build 28)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
-- synopsys translate_off
LIBRARY UNISIM;
USE UNISIM.all;
-- synopsys translate_on

ENTITY bus_error IS
   PORT( 
      am_error      : IN     std_logic;
      clk           : IN     std_logic;
      control_error : IN     std_logic;
      rst           : IN     std_logic;
      slot_error    : IN     std_logic;
      n_berr        : OUT    std_logic
   );

-- Declarations

END bus_error ;

--
ARCHITECTURE rtl OF bus_error IS
BEGIN
   process (clk , rst)
   begin
	   if rst = '1' then
		   n_berr <= 'Z';
	   elsif clk'event and clk = '1' then
			   if ((slot_error = '1') or (am_error = '1') or ( control_error = '1')) then
				   n_berr <= '0';
			   else
				   n_berr <= 'Z'; 
			   end if;
      end if;
   end process;
   
END rtl;

