 -- This block is a debounce and asyncrones to syncrones converter
 -- used in async_sync on most input signals.
--
-- VHDL Architecture vme_interface.synchroniser.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 09:15:37 08/07/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1a (Build 22)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY synchroniser IS
   PORT( 
      async : IN     std_logic;
      clk   : IN     std_logic;
      rst   : IN     std_logic;
      sync  : OUT    std_logic
   );

-- Declarations

END synchroniser ;


-- hds interface_end
ARCHITECTURE rtl OF synchroniser IS
signal a, b : std_logic;

BEGIN
process (rst,clk)
begin
	if rst = '1' then
		sync <= '1';
		a <= '1';
		b <= '1';

	elsif clk'event and clk = '1' then
		a <= async; 
		b <= a;

		if ((async = a) and (async /= b)) then
		sync <= a;
		end if;
	


	end if;


end process;

END rtl;

