--
-- VHDL Architecture back_end_fpga.OR_8.rtl
--
-- Created:
--          by - st79.UNKNOWN (TE2MOZAMBIQUE)
--          at - 15:44:56 17/08/2004
--
-- using Mentor Graphics HDL Designer(TM) 2003.2 (Build 28)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY AND9 IS
   PORT( 
      I0 : IN     std_logic;
      I1 : IN     std_logic;
      I2 : IN     std_logic;
      I3 : IN     std_logic;
      I4 : IN     std_logic;
      I5 : IN     std_logic;
      I6 : IN     std_logic;
      I7 : IN     std_logic;
      I8 : IN     std_logic;
      O  : OUT    std_logic
   );

-- Declarations

END AND9 ;

--
ARCHITECTURE rtl OF AND9 IS
BEGIN
   O <= I0 AND I1 AND I2 AND I3 AND I4 AND I5 AND I6 AND I7 AND I8 after 1 ns;
END rtl;

