--
-- VHDL Architecture back_end_fpga.AND_2.rtl
--
-- Created:
--          by - st79.UNKNOWN (TE2MOZAMBIQUE)
--          at - 09:53:30 17/08/2004
--
-- using Mentor Graphics HDL Designer(TM) 2003.2 (Build 28)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY AND2 IS
   PORT( 
      I0 : IN     std_logic;
      I1 : IN     std_logic;
      O  : OUT    std_logic
   );

-- Declarations

END AND2 ;

--
ARCHITECTURE rtl OF AND2 IS
BEGIN
   O <= I0 AND I1 after 1 ns;
END rtl;

