--
-- VHDL Architecture vme_firmware.id_eprom_wr.rtl
--
-- Created:
--          by - st79.UNKNOWN (TE2BELIZE)
--          at - 14:11:31 01/06/04
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;
USE IEEE.VITAL_Timing.all;

ENTITY i2c_eprom_wr IS
   PORT( 
      CLK_80        : IN     std_logic;
      data_from_vme : IN     std_logic_VECTOR (31 DOWNTO 0);
      for_eprom_wr  : IN     std_logic;
      rst           : IN     std_logic;
      write         : IN     std_logic;
      data_to_eprom : OUT    std_logic_VECTOR (19 DOWNTO 0)
   );

-- Declarations

END i2c_eprom_wr ;
ARCHITECTURE rtl OF i2c_eprom_wr IS
BEGIN
process(clk_80, rst)
begin

If rst = '1' then

	data_to_eprom <= (others => '0'); 

elsif clk_80'event and clk_80 = '1' then
	
	If (write = '1' and for_eprom_wr = '1') then
		data_to_eprom <= data_from_vme(19 downto 0) after 1 ns;
	end if;

end if;
end process;

END rtl;

