--
-- VHDL Architecture VME_blockram.make_longer.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 14:16:39 04/29/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY make_longer IS
   PORT( 
      clk       : IN     std_logic;
      en_mux    : IN     std_logic;
      rst       : IN     std_logic;
      en_mux_in : OUT    std_logic
   );

-- Declarations

END make_longer ;
ARCHITECTURE rtl OF make_longer IS
BEGIN
process (clk,rst)
variable count : unsigned(4 downto 0);
begin
if rst = '1' then
 en_mux_in <= '0';
 count := "11011";

elsif clk'event and clk = '1' then
	If en_mux = '1' then
		count := "11011";
		en_mux_in <= '1';

	else
		
		If count /= 0 then
			count := count - 1;
			en_mux_in <= '1';
		else
			en_mux_in <= '0';
			
		end if;
	end if;	
end if;
end process;
END rtl;

