--
-- VHDL Architecture vme_interface.address_latch.rtl
--
-- Created:
--          by - ejf42.UNKNOWN (TE2BANGLADESH)
--          at - 14:23:51 08/12/02
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1a (Build 22)
--
-- hds interface_start
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY latch IS
   GENERIC( 
      path_width : integer := 32
   );
   PORT( 
      clk       : IN     std_logic;
      latch     : IN     std_logic;
	  en		: IN	 std_logic;
      path_in_a : IN     std_logic_vector (path_width - 1 DOWNTO 0);
      rst       : IN     std_logic;
      path_out  : OUT    std_logic_vector (path_width - 1 DOWNTO 0)
   );

-- Declarations

END latch ;


-- hds interface_end
ARCHITECTURE rtl OF latch IS
BEGIN

process (clk, rst)
begin
if rst = '1' then
path_out <= (others => '0');

elsif clk'event and clk = '1' then
	 if en = '1' then
 		if latch = '1' then
			path_out <= path_in_a;
		end if;
   	end if;
end if;
end process;
END rtl;

