Delay FPGA: Device utilization summary: Number of External IOBs 71 out of 88 80% Number of LOCed External IOBs 71 out of 71 100% Number of RAMB16s 4 out of 4 100% Number of SLICEs 254 out of 256 99% Number of BUFGMUXs 9 out of 16 56% Number of DCMs 4 out of 4 100% Number of TBUFs 40 out of 128 31% Logic Utilization: Number of Slice Flip Flops: 348 out of 512 67% Number of 4 input LUTs: 226 out of 512 44% Logic Distribution: Number of occupied Slices: 254 out of 256 99% Number of Slices containing only related logic: 240 out of 254 94% Number of Slices containing unrelated logic: 14 out of 254 5% Total Number 4 input LUTs: 301 out of 512 58% Number used as logic: 226 Number used as a route-thru: 31 Number used as Shift registers: 44 Number of bonded IOBs: 71 out of 88 80% IOB Flip Flops: 68 IOB Dual-Data Rate Flops: 20 Number of Tbufs: 40 out of 128 31% Number of Block RAMs: 4 out of 4 100% Number of GCLKs: 9 out of 16 56% Number of DCMs: 4 out of 4 100% Number of RPM macros: 1 Total equivalent gate count for design: 298,636 Additional JTAG gate count for IOBs: 3,408 Peak Memory Usage: 58 MB Back End FPGA: Device utilization summary: Number of External DIFFMs 9 out of 228 3% Number of External DIFFSs 9 out of 228 3% Number of External IOBs 346 out of 456 75% Number of LOCed External IOBs 346 out of 346 100% Number of RAMB16s 40 out of 56 71% Number of SLICEs 5600 out of 10752 52% Number of BUFGMUXs 5 out of 16 31% Number of DCMs 3 out of 8 37% Logic Utilization: Total Number Slice Registers: 5,772 out of 21,504 26% Number used as Flip Flops: 5,770 Number used as Latches: 2 Number of 4 input LUTs: 6,940 out of 21,504 32% Logic Distribution: Number of occupied Slices: 5,600 out of 10,752 52% Number of Slices containing only related logic: 5,600 out of 5,600 100% Number of Slices containing unrelated logic: 0 out of 5,600 0% Total Number 4 input LUTs: 7,142 out of 21,504 33% Number used as logic: 6,940 Number used as a route-thru: 202 Number of bonded IOBs: 364 out of 456 79% IOB Flip Flops: 249 IOB Master Pads: 9 IOB Slave Pads: 9 IOB Dual-Data Rate Flops: 157 Number of Block RAMs: 40 out of 56 71% Number of GCLKs: 5 out of 16 31% Number of DCMs: 3 out of 8 37% Number of RPM macros: 31 Total equivalent gate count for design: 2,744,594 Additional JTAG gate count for IOBs: 17,472 Peak Memory Usage: 181 MB Front End FPGA 1500: Device utilization summary: Number of External DIFFMs 1 out of 196 1% Number of External DIFFSs 1 out of 196 1% Number of External IOBs 128 out of 392 32% Number of LOCed External IOBs 128 out of 128 100% Number of RAMB16s 24 out of 48 50% Number of SLICEs 7678 out of 7680 99% Number of BUFGMUXs 4 out of 16 25% Number of DCMs 1 out of 8 12% Logic Utilization: Total Number Slice Registers: 7,303 out of 15,360 47% Number used as Flip Flops: 7,302 Number used as Latches: 1 Number of 4 input LUTs: 10,388 out of 15,360 67% Logic Distribution: Number of occupied Slices: 7,678 out of 7,680 99% Number of Slices containing only related logic: 7,581 out of 7,678 98% Number of Slices containing unrelated logic: 97 out of 7,678 1% Total Number 4 input LUTs: 11,549 out of 15,360 75% Number used as logic: 10,388 Number used as a route-thru: 585 Number used for 32x1 RAMs: 576 (Two LUTs used per 32x1 RAM) Number of bonded IOBs: 130 out of 392 33% IOB Flip Flops: 158 IOB Master Pads: 1 IOB Slave Pads: 1 IOB Dual-Data Rate Flops: 4 Number of Block RAMs: 24 out of 48 50% Number of GCLKs: 4 out of 16 25% Number of DCMs: 1 out of 8 12% Total equivalent gate count for design: 1,797,967 Additional JTAG gate count for IOBs: 6,240 Peak Memory Usage: 199 MB Front End FPGA 2000: Device utilization summary: Number of External DIFFMs 1 out of 228 1% Number of External DIFFSs 1 out of 228 1% Number of External IOBs 128 out of 456 28% Number of LOCed External IOBs 128 out of 128 100% Number of RAMB16s 24 out of 56 42% Number of SLICEs 7498 out of 10752 69% Number of BUFGMUXs 4 out of 16 25% Number of DCMs 1 out of 8 12% Logic Utilization: Total Number Slice Registers: 7,302 out of 21,504 33% Number used as Flip Flops: 7,301 Number used as Latches: 1 Number of 4 input LUTs: 9,940 out of 21,504 46% Logic Distribution: Number of occupied Slices: 7,498 out of 10,752 69% Number of Slices containing only related logic: 7,498 out of 7,498 100% Number of Slices containing unrelated logic: 0 out of 7,498 0% Total Number 4 input LUTs: 11,054 out of 21,504 51% Number used as logic: 9,940 Number used as a route-thru: 538 Number used for 32x1 RAMs: 576 (Two LUTs used per 32x1 RAM) Number of bonded IOBs: 130 out of 456 28% IOB Flip Flops: 159 IOB Master Pads: 1 IOB Slave Pads: 1 IOB Dual-Data Rate Flops: 4 Number of Block RAMs: 24 out of 56 42% Number of GCLKs: 4 out of 16 25% Number of DCMs: 1 out of 8 12% Total equivalent gate count for design: 1,794,520 Additional JTAG gate count for IOBs: 6,240 Peak Memory Usage: 206 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.