Welcome to TiddlyWiki created by Jeremy Ruston, Copyright © 2007 UnaMesa Association
CMS FED cluster algorithm discussions
AGATA-DS catchup
Contacted by Billy P.
Doing MEng project at Imperial. Data acquisition of imaging system. Recommended using Xilinx dev boards.
Moved te2vilinius to lab
Installed Intel® PRO/1000 PFDual Port Server Adapter
MPMC2 Requirements
EDK 9.1SP2
ISE 9.1SP3
PC: Windows XP Service Pack 2
Linux: Redhat Enterprise Linux with kernel versions of 2.4 or later.
Rob has Local Link I/O nearly working with MPMC2. Buses mixed up though.
Need to interface MicroBlaze
Adam has EDK custom PLB peripherals working
''UK SCMS Workpackages VRVS''
What is format of document? Length etc. Text + Task summaries + Gannt charts ?
Will consistency across WP help case? Editor.
FE chip and Tracker Power
References to CMS upgrade proposal docs
What did Atlas do?
''WP A''
FED need fast readout scheme to find high trigger rate effects.
Option drop custom Mezzanine
drop system definitions
WP A In excess of likely money available
Tables WP A SM Existing 82 New Tech 87 RA + Student 60 SM 229 SM
£725K £220K
''Actions''
Update Tables
Correct double counting for Dave Cussans
''VRVS Summary''
CERN Dave N. Costas, Claire, Chris, Geoff
RAL Bob
No Mark
My proposal for an agenda is
Summary of background, current status and issues (GH & discussion)
Status of work packages
Status of remainder of proposal
Work required to complete a proposal
Time scale for deliverables
Dec meeting Date 17 Oct papers submitted
Need > 2 weeks to review submission
Draft C
Draft detailed A
email B
Geoff wants to be "hand off" WP details
PPRP based on Atlas review...
Need short physics case
Review each WP individually
Funding for some R&D
Don't know where final funding would come from
Other Funding Agencies bids, Atlas was first. US starting.
CMS doesn't yet have clear picture of what to do or when to do it.
Jim CMS Upgrade Working Party being set up. Mandate unclear. How upgrade should be managed?
CERN DG 2015-2017 LHC machine shutdown for upgrade?
Geoff doing Overview section
History, Physics, Tracker, Trigger
Tracker ~ 70% upgrade
Costas Q upgrade ECAL electronics?
Bob End cap electronics worst affected should survive LHC => Barrel electronics ok for SLHC?
But Crystals (in EC?) irreparably damaged after 10 Y LHC
Geoff. Concern about WP. Too much effort being requested.
Don't imagine we will get a lot.
cf Atlas a lot from within Rolling Grants.
VRVS cut off owing to double booking!
''Phone call to Mark''
Minded to keep bid for effort at proposed level.
WP A format was based on T2K PPRP bid.
Agree to wait for further feedback from Geoff and Chris
Possible meeting week of July 30th
Action Need Gannt chart for FED.
''Office Equipment''
REXEL CB356E ELECTRIC OFFICE COMB BINDER
''Tweezers Nanoprobes''
Gave Rob updated funding requirements
''Quixtream Linux'' on te7kiribati server R12 lab
Try new Quixtream linux version Version 1.14
uninstall version 1.12
NB must be ''root''
rpm -e Qxtrm-Eth-UDP
no print out.
(to get sorted list of all rpms installed)
[esdg1@te7kiribati ~]$ rpm -qa | sort > installed-rpms.txt
Install v1.14
[root@te7kiribati Installation-Files]# rpm -ivh QxtrmUDP-1.14-0.i386.rpm
Preparing... ########################################### [100%]
1:QxtrmUDP ########################################### [100%]
[root@te7kiribati Installation-Files]#
NB new package name
[esdg1@te7kiribati ~]$ rpm -q QxtrmUDP
QxtrmUDP-1.14-0
Installs in /opt/
[esdg1@te7kiribati ~]$ ls /opt/Quixilica/
doc examples netlists software vhdl
Copy to home area
[esdg1@te7kiribati opt]$ cp -r Quixilica/ ~/
[esdg1@te7kiribati ~]$ ls Quixilica/
doc examples netlists software vhdl
Use laptops in office with Dual Monitors and PCs in lab.
SL Mtg Brainstorming, 4 hats
ml505_ddr2_xxp_150mhz_75mhz_jc-1a based on robs rh1 design
can access DDR2 via OPB
can access ll_data_gen DCR via OPB-DCR (must use latest ll_gen IP core ll_data_gen_v2_00_b not 2.00a !)
''ml505_ddr2_xxp_150mhz_75mhz_jc-1b''
just reconnect CDMAC DCR bus
design doesn't run at all!!
no print out
get red error led RR2 -> bus error?
''ml505_ddr2_xxp_150mhz_75mhz_jc-1c''
reconnect CDMAC to DCR bus
and
disconnect ll_data_gen from DCR
design loads ok but
back to reading $FFFFFFFF from DCR regs
Try connecting back CDMAC and ll_data_gen 2b to DCR bus
Again the design hangs with red led on
And XMD JTAG access is broken
Go back to before added ll_data_gen ip ml505_ddr2_xxp_150mhz_75mhz_jc-1
Call it ''ml505_ddr2_xxp_150mhz_75mhz_jc-1aa''
Try reading DCR registers in CDMAC
Seems to work!
myAddr = XPAR_MPMC2_DDR2_OC_150MHZ_X64_MT4HTF3264H_53E_0_CDMAC_1_DCR_BASEADDR;
dataRead[0] = * (volatile unsigned long *) myAddr;
xil_printf("-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x%X before read :0x%X\r\n", myAddr, dataRead[0]);
* (volatile unsigned long *) myAddr = 0x12000000;
dataRead[0] = * (volatile unsigned long *) myAddr;
xil_printf("-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x%X after read :0x%X\r\n", myAddr, dataRead[0]);
-- CDMAC DCR test --
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 before read :0x0
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 after read :0x12000000
OPB base address value for OPB DCR bridge is not important.
OPB DDR2 memory errors as before though
-- OK at addr 0x11000000 data expected 0x4567 read :0x4567
-- OK at addr 0x11000004 data expected 0x4567 read :0x4567
-- Error at addr 0x11000008 data expected 0x4567 read :0x0
-- Error at addr 0x1100000C data expected 0x4567 read :0x0
change clock ratios and increase memory size for both OPB and CDMAC
PARAMETER C_OPB_0_MPMC2_TO_PI_CLK_RATIO = 2
PARAMETER C_OPB_0_BRIDGE_TO_PI_CLK_RATIO = 2
PARAMETER C_CDMAC_1_BASEADDR = 0x10000000
PARAMETER C_CDMAC_1_HIGHADDR = 0x1FFFFFFF
PARAMETER C_CDMAC_1_MPMC2_TO_PI_CLK_RATIO = 2
PARAMETER C_CDMAC_1_DCR_BASEADDR = 0b0000000000
PARAMETER C_CDMAC_1_DCR_HIGHADDR = 0b0000111111
PARAMETER C_OPB_0_BASEADDR = 0x10000000
PARAMETER C_OPB_0_HIGHADDR = 0x1FFFFFFF
OPB DDR2 Memory access is fixed
-- OK at addr 0x11000000 data expected 0x4567 read :0x4567
-- OK at addr 0x11000004 data expected 0x4567 read :0x4567
-- OK at addr 0x11000008 data expected 0x4567 read :0x4567
-- OK at addr 0x1100000C data expected 0x4567 read :0x4567
And works over 256 MBytes
-- OK at addr 0x1F000000 data expected 0x4567 read :0x4567
-- OK at addr 0x1F000004 data expected 0x4567 read :0x4567
-- OK at addr 0x1F000008 data expected 0x4567 read :0x4567
-- OK at addr 0x1F00000C data expected 0x4567 read :0x4567
BUT DCR access is broken !
-- CDMAC DCR test --
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 before read :0xFFFFFFFF
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 after read :0xFFFFFFFF
Go back to
PARAMETER C_CDMAC_1_MPMC2_TO_PI_CLK_RATIO = 1
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 before read :0xFFFFFFFF
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 after read :0xFFFFFFFF
-- OK at addr 0x1F000000 data expected 0x4567 read :0x4567
-- OK at addr 0x1F000004 data expected 0x4567 read :0x4567
-- OK at addr 0x1F000008 data expected 0x4567 read :0x4567
-- OK at addr 0x1F00000C data expected 0x4567 read :0x4567
Go back to
PARAMETER C_CDMAC_1_BASEADDR = 0x10000000
PARAMETER C_CDMAC_1_HIGHADDR = 0x13FFFFFF
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 before read :0xFFFFFFFF
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 after read :0xFFFFFFFF
-- OK at addr 0x1F000000 data expected 0x4567 read :0x4567
-- OK at addr 0x1F000004 data expected 0x4567 read :0x4567
-- OK at addr 0x1F000008 data expected 0x4567 read :0x4567
-- OK at addr 0x1F00000C data expected 0x4567 read :0x4567
Go back to
PARAMETER C_OPB_0_BASEADDR = 0x10000000
PARAMETER C_OPB_0_HIGHADDR = 0x13FFFFFF
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 before read :0xFFFFFFFF
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 after read :0xFFFFFFFF
-- OK at addr 0x11000000 data expected 0x4567 read :0x4567
-- OK at addr 0x11000004 data expected 0x4567 read :0x4567
-- OK at addr 0x11000008 data expected 0x4567 read :0x4567
-- OK at addr 0x1100000C data expected 0x4567 read :0x4567
-- Error at addr 0x1F000000 data expected 0x4567 read :0x0
-- Error at addr 0x1F000004 data expected 0x4567 read :0x0
-- Error at addr 0x1F000008 data expected 0x4567 read :0x0
-- Error at addr 0x1F00000C data expected 0x4567 read :0x0
Go back to
PARAMETER C_OPB_0_MPMC2_TO_PI_CLK_RATIO = 2
PARAMETER C_OPB_0_BRIDGE_TO_PI_CLK_RATIO = 1
-- CDMAC DCR test --
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 before read :0xFFFFFFFF
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 after read :0xFFFFFFFF
-- OK at addr 0x11000000 data expected 0x4567 read :0x4567
-- OK at addr 0x11000004 data expected 0x4567 read :0x4567
-- OK at addr 0x11000008 data expected 0x4567 read :0x4567
-- OK at addr 0x1100000C data expected 0x4567 read :0x4567
-- OK at addr 0x11000010 data expected 0x4567 read :0x4567
-- OK at addr 0x11000014 data expected 0x4567 read :0x4567
-- OK at addr 0x11000018 data expected 0x4567 read :0x4567
-- OK at addr 0x1100001C data expected 0x4567 read :0x4567
-- OK at addr 0x11000020 data expected 0x4567 read :0x4567
-- OK at addr 0x11000024 data expected 0x4567 read :0x4567
Go back to
PARAMETER C_OPB_0_MPMC2_TO_PI_CLK_RATIO = 1
PARAMETER C_OPB_0_BRIDGE_TO_PI_CLK_RATIO = 1
should be back to ml505_ddr2_xxp_150mhz_75mhz_jc-1
can read DCR but OPB some memory access is broken
-- CDMAC DCR test --
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 before read :0x0
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A08000 after read :0x12000000
-- OK at addr 0x11000000 data expected 0x4567 read :0x4567
-- OK at addr 0x11000004 data expected 0x4567 read :0x4567
-- Error at addr 0x11000008 data expected 0x4567 read :0x0
-- Error at addr 0x1100000C data expected 0x4567 read :0x0
-- OK at addr 0x11000010 data expected 0x4567 read :0x4567
-- OK at addr 0x11000014 data expected 0x4567 read :0x4567
-- Error at addr 0x11000018 data expected 0x4567 read :0x0
-- Error at addr 0x1100001C data expected 0x4567 read :0x0
-- OK at addr 0x11000020 data expected 0x4567 read :0x4567
-- OK at addr 0x11000024 data expected 0x4567 read :0x4567
-- Error at addr 0x11000028 data expected 0x4567 read :0x0
ADC channel is 16 bits @ 100 MHz
1 ADC channel per Rocket IO
Hi Saeed, John
http://www.xilinx.com/esp/wired/index.htm#gsrd wired communications pages
http://www.xilinx.com/bvdocs/appnotes/xapp536.pdf
http://www.xilinx.com/bvdocs/appnotes/xapp535.pdf - this app note has a better explanation of what the ll data generator does.
https://secure.xilinx.com/webreg/register.do?group=gsrd – access to the VHDL – currently not downloading for me…
Regards, Rob
''Comments''
re xapp535 TFT LocalLink design ported to ML505
using simple UART , simple drivers s/w
using DCR OBP bridge cdmac control from micro blaze
and OBP for seeing registers from micro blaze
get readout from rs232
try FAE for support
use deep FIFOs instead of MPMC2 for testing?
''General''
Overview of Deliverable system
Inputs and Outputs
Physical Connections
''QA Docs''
Complete Project Cards External and Internal
Requirements explicit for Patrick to agree up front
Deliverables for 2 ADC channels Phase 1 4 ADC channels Phase 2 ?
List of Technical Documents
Work breakdown doc. Refer to Rob's Block Diagram. Move to Monitoring folder?
Map out Tasks to Schedule
include constraints especially holidays
Define Project Milestones
Intermediate demonstrations (possibly also for Patrick to test)
File weekly emails under Project Monitoring
Other Tasks
PC Quixtream Software application Help from John
~MPMC2 microblaze? Help from John
Equipment
Special cables to order?
''Alternatives?''
~PCIe readout via ~ML555??
ML505 - available now 2 Off;
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-V5-ML505-UNI-G&iLanguageID=1
http://www.xilinx.com/products/boards/ml505/docs.htm schematics etc
http://www.xilinx.com/products/boards/ml505/reference_designs.htm reference designs
ML555 - 12th July 2Off;
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-V5-ML555-G
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?iLanguageID=1&sGlobalNavPick=&sSecondaryNavPick=&category=-1212920
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?iLanguageID=1&sGlobalNavPick=&sSecondaryNavPick=&category=-1212920 schematics etc
Local Link Layer;
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=LocalLink_UserInterface
Dev board templates are stored in
D:\EDK\board\Avnet
etc
Can be copied from EDK 8 to 9
Last week with Oz completed installation of FEDs in USC.
Only couple of problem boards at CERN not booting. Oz holding TTCrx problem board.
Still can't find FED v1 boards (without ORx) ?
Karl doesn't need Ivan for fibre cabling in USC.
Suggest recovering Exception crates second half September.
The SLHC Expression of Interest had been submitted and it was necessary to proceed towards a TDR, around 2011-12, via a Letter of Intent and Technical Proposal. The expectation was to be taking data in 2015-16.
Upgrades projects were open to all CMS institutes although it was inevitable that the present communities would have large input. All Collaboration Board members should declare the interest of their Institutes before the September CMS Week, to the appropriate Project Manager and Chair of the Upgrade Steering Group.
There were various issues such as management structure and funding which needed to be explored. It was proposed to set up a Task Force with the hope of making an initial proposal in the September CMS Week. Suggestions for the members of the Task Force were invited.
RAL Chris , Mark
Reviewed Geoff's merged draft.
Outer Readout is now WP2
Geoff is Principal Investigator on bid.
Propose Geoff is also Work Package 2 Manager
Went through Work Package Yearly Tasks
Optical Link Work package being done in US
But need to keep Links to CERN Versatile Link and GBT project
Keep options open where possible in text
eg not Strips, Trigger possibilities
Mark is thinking more of "digital" binary readout as analogue is getting harder in finer processes.
Geoff is suggesting linking FE chip trigger to muon chamber signals? need binary pipeline?
Mark does design and spice simulations in tandem with RAL
RAL does chip layout
Keep effort distributed over tasks
Chris considered dropping interconnect activities?
John wants to reprofile FED effort
Possibility of Oz working on WP2?
Dave C to work on Bristol activities unless requested otherwise.
Deliverables can be Reports
Chris : FE chip will likely get go ahead => everything else will be squeezed out.
Chris: Q whether cttee will approve money spent in US?
Cost of US engineer £16K / month
Actions WP2
Mark : Merge latest tables into Geoff's document
Mark: Chris : Provide deliverables
Mark: Ask Geoff to provide Trigger link section
Mark: Ask Geoff about groups developing Hybrids
John: Provide FED Gannt chart Y123
John: Update tables to profile effort
John: Update FED section , more explicit links to FE chip (refer to nr sections), Test bench for FE chip, PMC success nr cards made etc, explain mezzanine concept, block to handle trigger signals??
Chris: provide resource costs, commercial sensors
All : Arrange another (phone) meeting
All : Consider descoping options
Phone conf Mark, Chris
Discussion Timeline
Coherent WPs
draft to Geoff by July 22
Prepare for down sizing
UK Funding
Feedback on WP
Chris thinks ASIC is strongest item.
Chris "decided" to work on this
FED added on to chip WP ? (Implication FED case is weak)
Keep FE Chip flexible Triggering functions
2+ Names for Engineers Mark P.
Module tests separate from
feedback to chip designers
System tests weaker case. Optimistic
Powering scheme with existing chips effort Dave C
Use of Dave C on FED? Didn't get chance to explain Dave Newbold's request to use Dave on FPGA!
''Thoughts''
Chris took control of this conference.
Looks to me as if ASIC is only item that is likely to survive bid process.
''Actions''
Add Personnel costing round numbers
Put names in tables
Add Gannt charts
Chris to edit and send me today.
Pass on to Geoff before weekend.
PPC access
Tried following but always read 0 eg with mfdcr(0) command?
Article: 77105
Subject: Re: DSOCM BRAM I/F Controller
From: Peter Ryser <peter.ryser@xilinx.com>
Date: Wed, 22 Dec 2004 18:25:49 -0800
Links: << >> << T >> << A >>
Include xpseudo_asm.h into your C source code to make mfdcr() and
mtdcr() available.
- Peter
OPB_DCR access to ll_gen DCR working
''** FIX **''
''Changed ll_gen IP core ''
ll_data_gen to ll_data_gen_v2_00_b (was 2.00a)
Can now read DCR values !!
-- myAddr = DATAGEN_B2T1 0xD0000018 read :0xF5D74
ll_data_gen_v2_00_b
D:\MPMC2\mpmc2_release_20070610\data\misc_pcores
From OPB to PLB Doc
7.As a minimum, C_DCR_BASEADDR must have the two least significant bits set to a zero. C_DCR_HIGHADDR must be at least C_DCR_BASEADDR + 3 (because DCR addresses are always word addresses), and the two least significant bits must be set to a one. These parameters are used to determine the number of most significant address bits the bridge uses to decode its DCR register address space. These parameters allow the user to trade-off DCR address space resolution with size and speed of the bridge. If the user specifies a value for C_DCR_HIGHADDR that is greater than the minimum value, the range specified by C_DCR_BASEADDR and C_DCR_HIGHADDR should encompass a complete, contiguous power of two range (i.e. range = 2n, with the n least significant bits of C_DCR_BASEADDR set to zero). For example, if C_DCR_BASEADDR is set to 010h, then legal values for C_DCR_HIGHADDR are 013h, 017, or 01Fh. The number of upper address bits decoded to select the bridge would be 8, 7, or 6, respectively. The first case results in the most efficient use of DCR address space at the expense of additional FPGA resources and possibly reduces the maximum frequency at which the bridge can operate. The last case uses fewer FPGA resources which may also result in a faster implementation, but the bridge registers are aliased within those 16 locations, preventing the use of those redundant 13 locations of DCR address space for anything else. These parameters are ignored when C_OPB_REG_INTFC is set to 1.
8.There is no default value for C_DCR_BASEADDR or C_DCR_HIGHADDR to ensure the user specifies these values. If the user fails to specify these values a compiler error will result. If C_OPB_REG_INTFC is set to 1 then these parameters should be set to "0000000000".
Orders
ndustrial Computer Products (ICP)
http://www.icp-epia.co.uk/
Order Inventory:
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Quantity: 4
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Quantity: 2
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Base System Builder
Reference clock generates a DCM
Processor clock must be an integer multiple of Processor Bus clock
'Problem:''
Loading BitStream in XPS
Address Map for Processor microblaze_0
(0b0000000000-0b0000111111)
mpmc2_ddr2_oc_150mhz_x64_mt4htf3264h_53e_0 opb_v20_0->opb2dcr_bridge_0->dcr_v29_
0
(0000000000-0x00003fff) lmb_bram_if_cntlr_0 lmb_v10_1
(0000000000-0x00003fff) lmb_bram_if_cntlr_1 lmb_v10_0
(0x10000000-0x13ffffff) mpmc2_ddr2_oc_150mhz_x64_mt4htf3264h_53e_0 opb_v20_0
(0x40600000-0x4060ffff) opb_uartlite_0 opb_v20_0
(0x41400000-0x4140ffff) opb_mdm_0 opb_v20_0
Initializing Memory...
Checking ELFs associated with MICROBLAZE instance microblaze_0 for overlap...
ERROR:MDT - Failed to open elf file first_test_rh/executable.elf for reading
Implies memory map is wrong for executable
'Fix:''
Remove app from BRAM
and use bootloop in BRAM
'Problem:''
No print out to terminal
'Fix:''
Check baud rate in Terminal emulator
Check UART baud in mhs
Check Software Platform Settings
OS and Libraries
''standalone stdout and stdin are using correct UART in design ''
''Problem:''
Building Directory Structure for microblaze_0
ERROR:MDT - Failed to create directory
E:\WORKSPACES\ML505_Johns_Tests\ml505_ddr2_xxp_150mhz_75mhz_uarlite\microblaz
e_0\code\.
LibGen Done.
rm: cannot remove directory `code': Device or resource busy
make: *** [microblaze_0/lib/libxil.a] Error 2
'Fix:''
Quit out of XMD debugger
''Problem:''
uartlite printing gibberish characters to terminal
'Fix:''
In MHS opb_uartlite set CLK FREQ to one of the DCM clocks in the design
PARAMETER C_CLK_FREQ = 75000000
(was 100000000 from another design)
At least I think this is what fixed it!
''Problem:''
Release 9.1.02i - Map J.33
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
Using target part "5vlx50tff1136-1".
ERROR:Map:168 - Output file "system_map.ncd" already exists. Please specify -w
to overwrite.
ERROR:Map:151 - Problem encountered parsing the command line.
''Fix:''
Delete system_map.ncd in Implementation/ and rerun
''Problem:''
Analyzing file E:\johnc\WORKSPACES\fpga-ref-designs\MPMC2\ml505_ddr2_xxp_150mhz_75mhz\microblaze_0\code\ddr_mem_test.elf...
At Local date and time: Fri Jul 27 08:42:37 2007
xbash -q -c "cd /cygdrive/e/johnc/WORKSPACES/fpga-ref-designs/MPMC2/ml505_ddr2_xxp_150mhz_75mhz/; /usr/bin/make -f system.make download; exit;" started...
make: *** No rule to make target `microblaze_0/code/xmdstub.elf', needed by `implementation/download.bit'. Stop.
''Fix:''
Means xmdstub.elf is missing from design
Copy xmd.stub files from another project (using same dev board / FPGA?)
''microblaze_0/code/''
xmdstub.elf
xmdstubaddr.s
make.xmdstub
xmdstub.s
''Problem:''
In XMD using Microblaze
Cannot download elf file
''Fix:''
In XPS Applications panel
Enabled ''microblaze_0_xmdstub'' in BRAM
(instead of microblaze_0_bootloop)
because unlike PPC the Microblaze doesn't have hardwired XMD interface?
''but in ML505 bsb app test bootloop was in BRAM and yet could download elf ???''
same in ML403 MPMC2 example?
''Problem:''
Done!
At Local date and time: Fri Jul 27 16:34:51 2007
xbash -q -c "cd /cygdrive/e/johnc/WORKSPACES/fpga-ref-designs/MPMC2/ml403_ddr_idpoc_100mhz/; /usr/bin/make -f system.make program; exit;" started...
make: *** No rule to make target `../../sw/headers/globes_16frames.bmp.h', needed by `ScreenTest/executable.elf'. Stop.
''Fix:''
Copy globes_16frames.bmp.h from another ML403 project
and put in new sw/headers/ folder 2 levels up from project!!
Better to fix makefile somehow
Compiler
Optimisation level O2 removes dead loops from code.
Xilinx EDK HOWTO 4
This HOWTO discusses some aspects of the OPB bus.
* Memory IO Code
* Memory Address Offsets
Note: This HOWTO uses Xilinx EDK version 9.1i
http://www.bioinspired.com/users/ajg112/electronics/edkHOWTO4.shtml
Changing Marks for BRAM enable for Apps causes complete design to be resynthesised??
Edit MHS file and SAVE recreates System Assembly view
for printf use:
xil_printf("-- Errors:0x%X\r\n", errors);
To get XMD debugger shell to work with unix like commands rather than dos (eg ls rather than dir)
make sure %XILINX_EDK%/cygwin/bin executable path is in Windows PATH environment variable
(also needed for MPMC2 GUI Tool)
to verify
dos shell console>sed -V
shows GNU version
Customer Focus flip charts
Brainstorming, 4 hats
Hidden assets
FAE
Laptops in offices with Dual Monitors + PC in lab with Dual Monitors
Water leak at rack.
''History''
2001 – 2003 Electronic system design graduate training scheme.
Dispute at end of Graduate Training with RS at review of scheme meeting
Ed believes his move to band 5 was delayed because of this by 1 month and his RRA delayed by 5 months
Ed believes LM gave insufficient support
2nd "dispute" with another Training event (RS brother in law?) . Further meeting with RS.
Paul Seller is member of panel not Ed's technical expert
Viraj not available week before
Tim not available week before
Marcus not available week before
Renato present
Clive ??
Dave S present
JVM present
Ian T ??
Miriam present
Expert?
Folder properties
Sharing
Permissions
Add
Location CLRC
Object Name jac36
Full access
''access to esdg group home files"
ssh to eclair
telnet to fudge
bash
cd /esdg/ejf42
''Billing Address from 09/05/2007''
STFC, C/O Jackie Standbridge
STBU, R68, 2.14
RAL
HSIC
Didcot
Oxon
OX11 0QX
''Limits from 17/07/2006''
maximum single transaction value £5,000
monthly limit £10,000
''Authorising Manager''
Rob
''TBU Finance''
R25 1.22
STBU Finance Group Mailbox
''Procurement Limits''
Low value orders < £5K use GPC
£5K < Orders < £25K Requisition : Min 2 quotations or Quotation + Single source case
£25K < Orders < £154K Requisition + Spec + List of suppliers ; Procurement formal competitive tender
Orders > £154K EC Procurement rules
Budget £80,000
Assumed 20 unfunded (may be much less so get more budget)
Aim for ML505 each
Risk assessment web link and password
MI3 using Rob's EDK dual port memory design
AGATA-DS
ADC source output on Rocket I/O
rpms?
cable as per NAPS 1.5m connector v short cable up to 1 GHz
Training pattern for V5 Chipsync ?
v large Portfolio of Xilinx IP. Training Ed?
Local Link layer for our IP design interconnect?
MPMC2 generate pcore button -> Verilog files and EDK files (copy to EDK installation area and appear in project)
Problems with dialect of Verilog
Put in VHDL top level design. Netlists rather than Verilog.
Generates Peripheral Analyser? , MPD file order for XST
Connect PCIe?
Customer Focus 2
Collate summary CF1 docs SL?
Short dedicated group meeting to review summary
Rob: Use existing QA to implement Business Process improvements
Design Cttee is now a QA Project with Local Instructions, Problem reports
Azmat: Consider elog for problem reports?
Design Committee Ed
Submit material!
Check web pages for advice
Saeed
Audit Training soon
VHDL training book
MICE talk Senerath ; interface block diagram was nice
Tim N is doing software for MICE
Rig is next to R12 lab
Disposable Soma, Egg Hen Egg
Company Hidden Assets UK plc , English language , Services Industry
Phone conversation with Nadal Customer Support 9/7/07
Confirmed my original technical problem is resolved.
End users do not need license (if they are not developing).
He will provide quotes for Linux Floating license 32 bit Bundled Linux and Windows Floating licenses
Academic discount of 30%
UK distributor exists but direct from Jungo better
DMA support PCI express support
cc Nadal if further technical queries
Order placed by fax 12/07/07
Windows and Linux Floating research package incl 12 months support
Quote Total US $6,948
Uses Virtex 5 Engineering Sample
XC5VLX50T
1C-ES
Faxed credit card details to Jayne Spiby for ML555 cables x 2 order
''ml505_ddr2_xxp_150mhz_75mhz'' design for MPMC2 on ML505
''Set Compiler Options''
Using default linker script (Don't know where this is?)
Program Start 0x10000100 => in DDR via XCL MPMC2 (see address map below)
Stack 0x400 (in BRAM via LMB?)
Heap 0x400
''XPS''
Build application
mb-gcc -O2 sw/ddr_mem_test/src/ddr_mem_test.c -o microblaze_0/code/ddr_mem_test.elf \
-Wl,-defsym -Wl,_TEXT_START_ADDR=0x10000100 -Wl,-defsym -Wl,_STACK_SIZE=0x400 -Wl,-defsym -Wl,_HEAP_SIZE=0x400 -mno-xl-soft-mul -mxl-pattern-compare -mcpu=v6.00.b -g -I./microblaze_0/include/ -L./microblaze_0/lib/ \
Address Map for Processor microblaze_0
(0b0010000010-0b0010000011) plb_tft_cntlr_ref_0 opb_v20_0->opb2dcr_bridge_0->dcr_v29_0
(0000000000-0x00003fff) lmb_bram_if_cntlr_0 lmb_v10_1
(0000000000-0x00003fff) lmb_bram_if_cntlr_1 lmb_v10_0
(0x10000000-0x1fffffff) mpmc2_0 opb_v20_0->opb2plb_bridge_0->plb_v34_0
(0x10000000-0x1fffffff) mpmc2_0 microblaze_0_IXCL
(0x10000000-0x1fffffff) mpmc2_0 microblaze_0_DXCL
(0x20000000-0x200fffff) opb_emc_0 opb_v20_0
(0x28000000-0x29ffffff) opb_emc_0 opb_v20_0
(0x41400000-0x4140ffff) opb_mdm_0 opb_v20_0
(0xa0000000-0xa0001fff) opb_uart16550_0 opb_v20_0
(0xd1000fc0-0xd1000fdf) opb_intc_0 opb_v20_0
NB MUST enable BRAM microblaze_0_xmdstub
Populating list of memories for processor microblaze_0...
Get Program Size menu option
Analyzing file E:\WORKSPACES\fpga-dev-board-ref-designs\MPMC2\ml505_ddr2_xxp_150mhz_75mhz\microblaze_0\code\ddr_mem_test.elf...
At Local date and time: Thu Jul 26 13:41:28 2007
xbash -q -c "cd /cygdrive/e/WORKSPACES/fpga-dev-board-ref-designs/MPMC2/ml505_ddr2_xxp_150mhz_75mhz/; mb-size E:/WORKSPACES/fpga-dev-board-ref-designs/MPMC2/ml505_ddr2_xxp_150mhz_75mhz/microblaze_0/code/ddr_mem_test.elf; exit;" started...
text data bss dec hex filename
10317 100 2080 12497 30d1 E:/WORKSPACES/fpga-dev-board-ref-designs/MPMC2/ml505_ddr2_xxp_150mhz_75mhz/microblaze_0/code/ddr_mem_test.elf
=> > 16K size of LMB BRAM
Xilinx Microprocessor Debug (XMD) Engine
Xilinx EDK 9.1.02 Build EDK_J_SP2.4
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
''XMD%''
Processor(s) in System ::
Microblaze(1) : microblaze_0
Address Map for Processor microblaze_0
(0b0010000010-0b0010000011)
plb_tft_cntlr_ref_0 opb_v20_0->opb2dcr_bridge_0->dcr_v29_0
(0000000000-0x00003fff) lmb_bram_if_cntlr_0 lmb_v10_1
(0000000000-0x00003fff) lmb_bram_if_cntlr_1 lmb_v10_0
(0x10000000-0x1fffffff) mpmc2_0 opb_v20_0->opb2plb_bridge_0->plb_v34_0
(0x10000000-0x1fffffff) mpmc2_0 microblaze_0_IXCL
(0x10000000-0x1fffffff) mpmc2_0 microblaze_0_DXCL
(0x20000000-0x200fffff) opb_emc_0 opb_v20_0
(0x28000000-0x29ffffff) opb_emc_0 opb_v20_0
(0x41400000-0x4140ffff) opb_mdm_0 opb_v20_0
(0xa0000000-0xa0001fff) opb_uart16550_0 opb_v20_0
(0xd1000fc0-0xd1000fdf) opb_intc_0 opb_v20_0
Info:AutoDetecting cable. Please wait.
Info:Connecting to cable (Parallel Port - LPT1).
Info:Checking cable driver.
Info: Driver windrvr6.sys version = 9.0.0.0.Info: WinDriver v9.00 Jungo (c) 1997
- 2007 Build Date: Mar 27 2007 X86 32bit SYS 13:58:07, version = 900.
No resources.
Info: LPT base address = 0378h.
Info: ECP base address = 0778h.
Info:Cable connection failed.
Info:Connecting to cable (Parallel Port - LPT2).
Info:Checking cable driver.
Info: Driver windrvr6.sys version = 9.0.0.0.Info: WinDriver v9.00 Jungo (c) 1997
- 2007 Build Date: Mar 27 2007 X86 32bit SYS 13:58:07, version = 900.
Info:Cable connection failed.
Info:Connecting to cable (Parallel Port - LPT3).
Info:Checking cable driver.
Info: Driver windrvr6.sys version = 9.0.0.0.Info: WinDriver v9.00 Jungo (c) 1997
- 2007 Build Date: Mar 27 2007 X86 32bit SYS 13:58:07, version = 900.
Info:Cable connection failed.
Info:Connecting to cable (Parallel Port - LPT4).
Info:Checking cable driver.
Info: Driver windrvr6.sys version = 9.0.0.0.Info: WinDriver v9.00 Jungo (c) 1997
- 2007 Build Date: Mar 27 2007 X86 32bit SYS 13:58:07, version = 900.
Info:Cable connection failed.
Info:Connecting to cable (Usb Port - USB21).
Info:Checking cable driver.
Info: Driver xusbdfwu.sys version: 1021 (1021).
Info: Driver windrvr6.sys version = 9.0.0.0.Info: WinDriver v9.00 Jungo (c) 1997
- 2007 Build Date: Mar 27 2007 X86 32bit SYS 13:58:07, version = 900.
Calling setinterface num=0, alternate=0.
DeviceAttach: received and accepted attach for:
vendor id 0x3fd, product id 0x8, device handle 0x2e50038
Info: Cable PID = 0008.
Info: Max current requested during enumeration is 280 mA.
Info: Cable Type = 3, Revision = 0.
Info: Cable Type = 0x0605.
Info: Setting cable speed to 6 MHz.
Info:Cable connection established.
Info:Firmware version = 1021.
Info:CPLD file version = 0012h.
Info:CPLD version = 0012h.
JTAG chain configuration
--------------------------------------------------
Device ID Code IR Length Part Name
1 05059093 16 XCF32P
2 05059093 16 XCF32P
3 09608093 8 xc95144xl
4 0a001093 8 System_ACE
5 02a96093 10 XC5VLX50T_U
MicroBlaze Processor Configuration :
-------------------------------------
Version............................5.00.c
No of PC Breakpoints...............1
No of Read Addr/Data Watchpoints...0
No of Write Addr/Data Watchpoints..0
Instruction Cache Support..........off
Data Cache Support.................off
Exceptions Support................off
FPU Support.......................off
Hard Divider Support...............off
Hard Multiplier Support............off
Barrel Shifter Support.............off
MSR clr/set Instruction Support....on
Compare Instruction Support........on
Connected to MDM UART Target
Connected to "mb" target. id = 0
Starting GDB server for "mb" target (id = 0) at TCP port no 1234
XMD%
XMD% ls
README bootloops libgen.log sw system.mss
__xps data microblaze_0 synthesis system.xmp
_impactbatch.log etc pcores system.log system_incl.make
bitinit.log hdl platgen.log system.make
blkdiagram implementation platgen.opt system.mhs
XMD% dow microblaze_0/code/ddr_mem_test.elf
section, .vectors.reset: 0x00000000-0x00000007
section, .vectors.sw_exception: 0x00000008-0x0000000f
section, .vectors.interrupt: 0x00000010-0x00000017
section, .vectors.hw_exception: 0x00000020-0x00000027
section, .text: 0x10000100-0x100020fb
section, .init: 0x100020fc-0x10002127
section, .fini: 0x10002128-0x10002147
section, .ctors: 0x10002148-0x1000214f
section, .dtors: 0x10002150-0x10002157
section, .rodata: 0x10002158-0x1000293c
section, .data: 0x10002940-0x1000298f
section, .jcr: 0x10002990-0x10002993
section, .bss: 0x10002998-0x100031b7
Downloaded Program microblaze_0/code/ddr_mem_test.elf
Setting PC with Program Start Address 0x00000000
XMD%
jc0 variation of ml505 mem test with ml403 gsrd additions
jc1 variation of rh1
jc2 variation of rh2 connected local link gen to cdmac
MPMC2 Gui
Must not have any spaces in folder path !
Else Make Pcore operation fails
see Error Log in tool
Must add to PATH environment for cygwin
ML505 Ref design
ml505_ddr2_xxp_150mhz_75mhz
Microblaze DDR2 mem test using all 4 combinations of Data and Instruction Cache enables
ddr_mem_test.c
define MEM_SIZE 0x10000000 ''256 MB''
define BANK_ADDR_BITS 0x0C000000 // Address Location of Bank Address Bits
define ROW_ADDR_BITS 0x03FFE000 // Address Location of Row Address Bits
define COL_ADDR_BITS 0x00001FF8 // Address Location of Col Address Bits
define MEM_OFFSET 0x10000000 ''256 MB''
unsigned long memOffset=MEM_OFFSET;
unsigned long startAdr=MEM_OFFSET + 0x100000;
unsigned long size=(MEM_SIZE)-0x100000-4;
DDR2 mem starts at Microblaze address offset 256MB
Size is 256MB
Skip first 1 MB where code and data is located! (see map below)
ddr_mem_test.elf make.xmdstub xmdstub.elf xmdstub.s xmdstubaddr.s
XMD% dow microblaze_0/code/ddr_mem_test.elf
section, .vectors.reset: 0x00000000-0x00000007
section, .vectors.sw_exception: 0x00000008-0x0000000f
section, .vectors.interrupt: 0x00000010-0x00000017
section, .vectors.hw_exception: 0x00000020-0x00000027
section, .text: 0x10000100-0x100020fb
section, .init: 0x100020fc-0x10002127
section, .fini: 0x10002128-0x10002147
section, .ctors: 0x10002148-0x1000214f
section, .dtors: 0x10002150-0x10002157
section, .rodata: 0x10002158-0x1000293c
section, .data: 0x10002940-0x1000298f
section, .jcr: 0x10002990-0x10002993
section, .bss: 0x10002998-0x100031b7
Downloaded Program microblaze_0/code/ddr_mem_test.elf
Setting PC with Program Start Address 0x00000000 ''start in LMB BRAM then jumps to code in DDR2"
''Terminal Output''
Pass # 0a, Memory Test Begins at Addr 0x10100000, Length = 0xFEFFFFC, ICache = O
ff, DCache = Off
LOG: TEST0 - Write all memory to zero, using word writes and check
Writing
Reading
LOG: TEST1 - Write all memory to Fs, using word writes and check
Writing
Reading
LOG: TEST2 - Testing for stuck together row/col bits
Clearing memory to zeros
Checking
LOG: Set all memory to 0x00110055 for next test
LOG: TEST3 - Testing for maximum ba/row/col noise
NOTE: This test performs 16 word writes followed by 16 word reads
NOTE: Each 64 bytes inverts the ba/row/col address
LOG: TEST4 - Testing for Inverse Data at Address, write all then read all
Total Number Errors = 0
Pass # 0b, Memory Test Begins at Addr 0x10100000, Length = 0xFEFFFFC, ICache = O
n, DCache = Off
LOG: TEST0 - Write all memory to zero, using word writes and check
Writing
Reading
LOG: TEST1 - Write all memory to Fs, using word writes and check
Writing
Reading
LOG: TEST2 - Testing for stuck together row/col bits
Clearing memory to zeros
Checking
LOG: Set all memory to 0x00110055 for next test
LOG: TEST3 - Testing for maximum ba/row/col noise
NOTE: This test performs 16 word writes followed by 16 word reads
NOTE: Each 64 bytes inverts the ba/row/col address
LOG: TEST4 - Testing for Inverse Data at Address, write all then read all
Total Number Errors = 0
Pass # 0c, Memory Test Begins at Addr 0x10100000, Length = 0xFEFFFFC, ICache = O
ff, DCache = On
LOG: TEST0 - Write all memory to zero, using word writes and check
Writing
pcores/mpmc2_.../hdl/verilog/
mpmc2.v
contains interface definitions generated for core and must match mpd file
ML505 Ref design using XCL breaks when do anything to MPMC2 params? or adding new MPMC2 core
MPMC2 core address generation 64 MB
ll_data_gen core version
Robs design uses OPB interface
Can't get OPB and DCR access to work reliably together?
UART s/w setting , interrupts
PIM clock speeds ?
Trying lots of different parameter settings.
Rebuilding after each parameter change is painful.
Negative Went down some blind alleys.
Positive Learning lot about EDK the hard way.
Took "working" design ml505_ddr2_xxp_150mhz_75mhz_uarlite2
dow mem_jac_test.elf start addr 0x10000100
mrd in XMD reads code in memory
removed PLB components and it broke
ml505_ddr2_xxp_150mhz_75mhz_uarlite2_noplb
dow mem_jac_test.elf start addr 0x10000100
mrd in XMD always reads 0's
access to DDR2 is not working
Running mem_test_jac with design ml505_ddr2_xxp_150mhz_75mhz_uarlite
start addr 0x00000100
Can write and read to addresses in DDR2 via MPMC2 Ok
eg
0x00000000
0x12000000
0x1f000000
and can see changes in Memory View display
mem_test_jac also runs with start address 0x10000100 ie in MPMC2 memory
Run same program with design ml505_ddr2_xxp_150mhz_75mhz_uarlite_noplb_cdmac_llgen
Doesn't work. Always read 0's from memory.
ml505_ddr2_xxp_150mhz_75mhz_uarlite_noplb
Doesn't work. Always read 0's from memory.
Seems like design problems started on removing PLB bus??
Copy ml505_ddr2_xxp_150mhz_75mhz_uarlite to ml505_ddr2_xxp_150mhz_75mhz_uarlite2
Leave PLB bus
Add new MPMC2 core as for ml505_ddr2_xxp_150mhz_75mhz_uarlite_noplb_cdmac in [[More MPMC2 trials]]
ml505_ddr2_xxp_150mhz_75mhz_uarlite2_cdmac
Platgen ??
ERROR:MDT - INST:mpmc2_ddr2_xxc_150mhz_x64_mt4htf3264h_53e_0
PORT:MPMC2_0_DDR2_CE_O CONNECTOR:ddr2_cke -
E:\WORKSPACES\ML505_Johns_Tests\ml505_ddr2_xxp_150mhz_75mhz_uarlite2_cdmac\sy
stem.mhs line 302 - 2 bit-width connector assigned to 1 bit-width port
ERROR:MDT - INST:mpmc2_ddr2_xxc_150mhz_x64_mt4htf3264h_53e_0
PORT:MPMC2_0_DDR2_ODT_O CONNECTOR:ddr2_odt -
E:\WORKSPACES\ML505_Johns_Tests\ml505_ddr2_xxp_150mhz_75mhz_uarlite2_cdmac\sy
stem.mhs line 302 - 2 bit-width connector assigned to 1 bit-width port
Completion time: 0.00 seconds
ERROR:MDT - platgen failed with errors!
Cause of error parameter
PARAMETER C_MPMC2_0_MEM_CLK_WIDTH was not defined
should be 2
see MPMC2 doc Table 1-7 p 63
Took mhs from previous design ml505_ddr2_xxp_150mhz_75mhz_uarlite2 and just pasted in new CDMAC part.
Commented out PLB PIM ports.
Added dummy plb_central_dma for PLB slave
Builds
mem_test_jac still runs with start address 0x10000100 ie in MPMC2 memory
Conclude problem with writing and reading MPMC2 DDR2 memory and running app in DDR2 at 0x10000100 are related.
Add ll_data_gen core v 2.00a
follow steps for
ml505_ddr2_xxp_150mhz_75mhz_uarlite_noplb_cdmac_llgen
Broken again!!!
mem_test_jac doesnt' run with start address 0x10000100 and Always read 0's from memory.
Tried ml505_ddr2_xxp_150mhz_75mhz_uarlite2_cdmac again
Now this is broken too!!! was working?
Tried downloading mem_test_elf from working design. Also fails -> problem is hw bit stream.
Don't understand why ??!! Maybe didn't load bit stream and ran with old bitstream and thought was working?
Rebuilding app? Library Generator?
Linker map?
[file:///E|/GENERAL REFERENCE\FPGA XILINX Docs\Multi Port Memory Controller\mpmc2_release_20070610\docs]
11. Note: During memory initialization (following reset), the memory physical interface writes to the
bottom locations in memory to set up the write training pattern. This can affect addresses between
0x00000000 and 0x000000FF. Therefore, after reset, these locations in memory will be
overwritten. It is recommended that user SW code stored in memory not start at address
0x0000000 of the memory. SW code should start at an address that is 0x100 offset into memory
and the boot vector set to jump to this offset address. For example, a PPC405 system would be set
to boot at 0xFFFFFFFC and then jump to 0x00000100 in memory to start executing code out of
memory. As an example, look at the SW compile options in the MPMC2 reference designs.
ML403 design doesn't seem to work
TFT display or DDR memory test
ML505 memory test works
uses microblaze
ODB to DCR registers
Insert Local Link gen
Insert TFT controller
Like Rob start with ML505 MPMC2 memory test design
ml505_ddr2_xxp_150mhz_75mhz
Copy elements from MPMC2 GSRD
ml403_ddr_idpoc_100mhz_gsrd
copied to pcores directory
ll_data_gen_v2_00_a
ll_tft_cntlr_v2_00_a
edited mhs
Added
ll_data_gen
ll_tft_cntrl
Keep microblaze XSL ports for memory test
copy CDMAC part from mpd file (for consistent MPMC2 ports interface)
mpmc2_ddr_idpoc_100mhz_x16_hyb25d256160bt_7_v2_1_0.mpd
saved mhs file
saw changes in System Assembly bus map
Remove plb tft ctrl
Set DCR base addressess in MHS file
Need to change accordingly in example code
Removed PLB bus from design
Removed PLB port from MPMC2
Had to set clocks for MPMC2 CDMAC to 200 MHz (was 100 MHz in V4 reference design)
Clocks for LL Gen 75 MHz?
Nb for Microblaze on ML505 we have
OPB MDM Microprocessor Debug Module for microblaze
in MHS and MSS (driver type uartlite)
Remove OPB EMC not needed
Monthly chat
Rapport
Advice
No formal contracts
Line manager
RISC
Registers 32 GP
Load and Store
Pipeline
32 bit instructions
Harvard Memory Architecture Instruction / Data Separate spaces but can overlap
Interfaces XCL via cache ; OPB bus ; LMB to BRAM
Cache is selectable
Stack and Heap in same space
(Heap size is ignored in XPS)
ml505_ddr2_xxp_150mhz_75mhz_uarlite
MicroBlaze Processor Configuration :
-------------------------------------
Version............................6.00.b
No of PC Breakpoints...............1
No of Read Addr/Data Watchpoints...0
No of Write Addr/Data Watchpoints..0
Instruction Cache Support..........on
Instruction Cache Base Address.....0x10000000
Instruction Cache High Address.....0x1fffffff
Data Cache Support.................on
Data Cache Base Address............0x10000000
Data Cache High Address............0x1fffffff
Exceptions Support................on
FPU Support.......................off
Hard Divider Support...............off
Hard Multiplier Support............on - (Mul32)
Barrel Shifter Support.............off
MSR clr/set Instruction Support....on
Compare Instruction Support........on
Connected to MDM UART Target
Connected to "mb" target. id = 0
Starting GDB server for "mb" target (id = 0) at TCP port no 1234
XMD%
XMD% pwd
E:/WORKSPACES/ML505_Johns_Tests/ml505_ddr2_xxp_150mhz_75mhz_uarlite
XMD% cd microblaze_0/code
XMD% ls
mem_test_jac.elf
XMD% dow mem_test_jac.elf
section, .vectors.reset: 0x00000000-0x00000003
section, .vectors.sw_exception: 0x00000008-0x0000000b
section, .vectors.interrupt: 0x00000010-0x00000013
section, .vectors.hw_exception: 0x00000020-0x00000023
section, .text: 0x00000100-0x00001117
section, .init: 0x00001118-0x0000113b
section, .fini: 0x0000113c-0x00001157
section, .ctors: 0x00001158-0x0000115f
section, .dtors: 0x00001160-0x00001167
section, .rodata: 0x00001168-0x00001590
section, .data: 0x00001598-0x000015d3
section, .jcr: 0x000015d4-0x000015d7
section, .bss: 0x000015d8-0x00001de7
Downloaded Program mem_test_jac.elf
Setting PC with Program Start Address 0x00000000
MicroBlaze Processor Configuration :
-------------------------------------
Version............................6.00.b
No of PC Breakpoints...............1
No of Read Addr/Data Watchpoints...0
No of Write Addr/Data Watchpoints..0
Instruction Cache Support..........on
Instruction Cache Base Address.....0x10000000
Instruction Cache High Address.....0x1fffffff
Data Cache Support.................on
Data Cache Base Address............0x10000000
Data Cache High Address............0x1fffffff
Exceptions Support................on
FPU Support.......................off
Hard Divider Support...............off
Hard Multiplier Support............on - (Mul32)
Barrel Shifter Support.............off
MSR clr/set Instruction Support....on
Compare Instruction Support........on
Connected to MDM UART Target
Connected to "mb" target. id = 0
Starting GDB server for "mb" target (id = 0) at TCP port no 1234
XMD% pwd
E:/WORKSPACES/ML505_Johns_Tests/ml505_ddr2_xxp_150mhz_75mhz_uarlite_noplb
XMD% ls
README data pcores system.log.bak
__xps etc platgen.log system.make
_impactbatch.log hdl platgen.opt system.mhs
bitinit.log implementation sw system.mss
blkdiagram libgen.log synthesis system.xmp
bootloops microblaze_0 system.log system_incl.make
XMD% cd microblaze_0/code
XMD% ls
mem_test_jac.elf
XMD% dow mem_test_jac.elf
section, .vectors.reset: 0x00000000-0x00000003
section, .vectors.sw_exception: 0x00000008-0x0000000b
section, .vectors.interrupt: 0x00000010-0x00000013
section, .vectors.hw_exception: 0x00000020-0x00000023
section, .text: 0x00000100-0x00001117
section, .init: 0x00001118-0x0000113b
section, .fini: 0x0000113c-0x00001157
section, .ctors: 0x00001158-0x0000115f
section, .dtors: 0x00001160-0x00001167
section, .rodata: 0x00001168-0x00001590
section, .data: 0x00001598-0x000015d3
section, .jcr: 0x000015d4-0x000015d7
section, .bss: 0x000015d8-0x00001de7
Downloaded Program mem_test_jac.elf
Setting PC with Program Start Address 0x00000000
Must set environment variable XIL_EDK_DISABLE_ARCH_SUPPORT_CHECK for PLB bus in V5
MPMC2 needs 200 MHz clock for memory
Step by step from MPMC2 ref design
''\ML505_Johns_Tests''
0) Try starting again with ML505 MPMC2 example design with XCL processor to memory
''Design ml505_ddr2_xxp_150mhz_75mhz''
ddr_mem_test working (nb serial terminal baud 57600 no parity)
microblaze_0_bootloop in BRAM
XDM printout
start addr = 0x10000100 in MPMC2 mem (see [[MPMC2 release notes]])
ddr_mem_test.elf
XMD% dow ddr_mem_test.elf
section, .vectors.reset: 0x00000000-0x00000007
section, .vectors.sw_exception: 0x00000008-0x0000000f
section, .vectors.interrupt: 0x00000010-0x00000017
section, .vectors.hw_exception: 0x00000020-0x00000027
section, .text: 0x10000100-0x100020fb
section, .init: 0x100020fc-0x10002127
section, .fini: 0x10002128-0x10002147
section, .ctors: 0x10002148-0x1000214f
section, .dtors: 0x10002150-0x10002157
section, .rodata: 0x10002158-0x1000293c
section, .data: 0x10002940-0x1000298f
section, .jcr: 0x10002990-0x10002993
section, .bss: 0x10002998-0x100031b7
Downloaded Program ddr_mem_test.elf
Setting PC with Program Start Address 0x00000000
Use simple test memory code app
print() doesn't work
1) Add UARTLITE to design in mhs
''Design ml505_ddr2_xxp_150mhz_75mhz_uarlite''
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x40601FFF (addr size could be much less, just 16 bytes?)
change PARAMETER C_CLK_FREQ = 75000000
lock other module addresses in system assembly
In System Assembly view
unconnect UART16550 Rx, Tx, Ir
connect UARTLITE Rx, Tx and link to external PORT edit in mhs (can do in system view too)
connect new Uart Ir to opb_intc port
40 mins just to route on te2vilnius! (doesn't usually take this long?)
rebuild
Use simple test memory code app
print() still doesn't work ??
Printing problem
In Software Platform Settings
OS and Libraries
standalone ''stdout'' and ''stdin'' were using old UART !! (same problem in Rob's design)
NB did NOT need to specify
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
not sure whether change to PARAMETER C_CLK_FREQ = 75000000 is needed?
Change Compiler Settings for mem_test_jac
Program Start Address to 0x00000100 to run in PLB BRAM (from 0x10000100)
Don't put mem_test_jac in BRAM keep bootloop in BRAM
Print Works.
Delete pcores and all assoc ports (int and ext), check synthesis one by one
OPB_16550 Synthesis ok
OPB_EMC (flash memory interface) (nb keeps flash_audio_reset_n port because common reset for other cores) Synthesis ok
PLB_TFT_CNTRL (synthesis complains must have one DCR slave, so connect to mpmc2 STATIC_PHY)
Generate bitstream
NgdBuild Errors could not find net(s) in the design
edit ucf file to remove NETs associated to removed cores
Builds ok Routing only 5 mins
Print not working ???
Rebooted ML505 to get boot program to print on terminal
Re downloaded mem_test_jac.elf
Print out working again!
Check memory accesses
XMD dow mem_test_jac.elf
Launch Software Debugger
Program output
-- before read from addr 0x -- PLB BRAM
-- data read :0xB8080100
-- after read from addr 0x --
-- before read from XPAR_OPB_UARTLITE_0_BASEADDR -- OPB Bus UART regs
-- data read :0x0
-- after read from XPAR_OPB_UARTLITE_0_BASEADDR --
-- before read from addr 0x10000000 -- DDR2 via MPMC2 XCL
-- data read :0xFFFFFFFF
use View Memory in debugger to verify these values in memory OK
2) Design ''ml505_ddr2_xxp_150mhz_75mhz_uarlite-noplb''
Disconnect PLB PIM from MPMC2 Synthesis errors must have at least 1 PLB slave
Delete pcores and all assoc ports (int and ext), check synthesis one by one
OPB2PLB Bridge (and remove connection to PLB PIM in MPMC2) Synthesis complains no PLB master
PLB with this removed as well
Synthesis OK but
ERROR:NgdBuild:756 - "system.ucf" Line 38: Could not find net(s)
'plb_v34_0_PLB_Rst' in the design. To suppress this error specify the
correct net name or remove the constraint.
Fix net and Rebuild OK
Test App memory works as before OK => using XCL access to MPMC2
Q. Microblaze memory map to various buses is determined by System Assembly Bus Address settings
XMD output..
Microblaze(1) : microblaze_0
Address Map for Processor microblaze_0
(0000000000-0x00003fff) lmb_bram_if_cntlr_0 lmb_v10_1
(0000000000-0x00003fff) lmb_bram_if_cntlr_1 lmb_v10_0
(0x10000000-0x1fffffff) mpmc2_0 microblaze_0_IXCL
(0x10000000-0x1fffffff) mpmc2_0 microblaze_0_DXCL
(0x40600000-0x40601fff) opb_uartlite_0 opb_v20_0
(0x41400000-0x4140ffff) opb_mdm_0 opb_v20_0
(0xd1000fc0-0xd1000fdf) opb_intc_0 opb_v20_0
Nb Microblaze can only access PLB via OBP2PLB bridge
3) Design ''ml505_ddr2_xxp_150mhz_75mhz_uarlite_noplb_cdmac''
Create new MPMC2 pcore with added CDMAC using MPMC2 GUI Tool
Start with ML505 reference 2 x XCL + PLB 3 PIMs change PLB to CDMAC keep clock 75 MHz
-> ''mpmc2_ddr2_xxc_150mhz_x64_mt4htf3264h_53e_v2_10_a''
Copy to design pcores folder
Need to close design and reopen to see new core in IP catalogue
(**)
Note XCL ADDR from core gen in MPD file = 0x0 to 0x03ffffff (64 MBytes at offset 0) ??
cf GUI addresses = 0x1000000 to 0x1FFFFFFF for Mem size = 256 MBytes
Remove
mpmc2_xxp... Synthesis errors eg microblaze_0 (microblaze) - The ICACHE XCL bus interface is unconnected.
NB Leave MPMC2 external ports in design eg to DDR2 !
Add
mpmc2_ddr2_xxc_150mhz_x64_mt4htf3264h_53e_v2_10_a
Connect XCL_0 to microblaze Inst
Connectc XCL_1 to microblaze Data
Connect CDMAC to DCR as slave (no STATIC PHY DCR connection)
Leave CDMAC LLSRC and LLDST unconnected
Many Synthesis errors for CDMAC eg PORT CDMAC_2_Clk must be connected in MHS.
Connect CDMAC LLSRC to LLDST
Many Synthesis errors for CDMAC eg PORT CDMAC_2_Clk must be connected in MHS.
Copy MPMC2 XCL mhs parameters and ports back from ml505_ddr2_xxp_150mhz_75mhz_uarlite design
In System Assembly Address Change CDMAC size to 256 MBytes and base addr to match XCL (**)
PARAMETER C_CDMAC_2_BASEADDR = 0x10000000
PARAMETER C_CDMAC_2_HIGHADDR = 0x1FFFFFFF
In System Assembly Address Change CDMAC DCR (set to 256 bytes as top register at word location $2F so allow at least $2F x 4 bytes = 188)
PARAMETER C_CDMAC_2_DCR_BASEADDR = 0b0000000000
PARAMETER C_CDMAC_2_DCR_HIGHADDR = 0b0000001111
Change to
PARAMETER C_CDMAC_2_MPMC2_TO_PI_CLK_RATIO = 2
as CDMAC PIM is clocked at half of memory frequency
In System Assembly view Ports:
Connect CDMAC_2_Clk to CLK_75MHz (must be equal or half of memory speed MPMC2_0_Clk0 = 150 MHz)
Connect CDMAC_2_CDMAC_INT to mpmc2_ddr2_xxc_150mhz_x64_mt4htf3264h_53e_0_CDMAC_2_CDMAC_INT (***)
Connect CDMAC_2_Rst to sys_rst_in
Build
Platform Gen
ERROR:MDT - INST:mpmc2_ddr2_xxc_150mhz_x64_mt4htf3264h_53e_0 PORT:MPMC2_0_Clk90
CONNECTOR:CLK_150MHz_90 -
E:\WORKSPACES\ML505_Johns_Tests\ml505_ddr2_xxp_150mhz_75mhz_uarlite_noplb_cdm
ac\system.mhs line 318 - No driver found!
BEGIN dcm_module
PORT CLK90 = CLK_150MHz_90 was removed somehow ?? put it back in MHS
WARNING:MDT - INST:mpmc2_ddr2_xxc_150mhz_x64_mt4htf3264h_53e_0
PORT:CDMAC_2_CDMAC_INT
CONNECTOR:mpmc2_ddr2_xxc_150mhz_x64_mt4htf3264h_53e_0_CDMAC_2_CDMAC_INT -
E:\WORKSPACES\ML505_Johns_Tests\ml505_ddr2_xxp_150mhz_75mhz_uarlite_noplb_cdm
ac\system.mhs line 342 - floating connection!
In System Assembly Ports Connect Interrupts Low to High dialog box Connect Uartlite and CDMAC interrupt to OPB_INTC controller
which is then connected to Microblaze interrupt input
generates following in mhs file
opb_intc
PORT Intr = opb_uartlite_0_Interrupt&mpmc2_ddr2_xxc_150mhz_x64_mt4htf3264h_53e_0_CDMAC_2_CDMAC_INT
Builds OK
Test App reads memory OK
Debugger can't change memory value in MPMC2 ?
OPBMDM needs PLB access via OBP PLB bridge ?
Change mem_test_jac to do simple write zeros to MPMC2 memory and check back
Passes memory test
4) Design ''ml505_ddr2_xxp_150mhz_75mhz_uarlite_noplb_cdmac_llgen''
Add Local Link Generator (Source) and Local Link TFT display controller (Destination)
From
E:\WORKSPACES\fpga-dev-board-ref-designs\MPMC2\projects\ml403_ddr_idpoc_100mhz_gsrd\pcores
ll_data_gen_v2_00_a
ll_tft_cntlr_v2_00_a
D:\MPMC2\mpmc2_release_20070610\data\misc_pcores\
ll_data_gen_v2_00_b
Add to design pcores
Project Rescan User Repositories
System Assembly Add IP ll_data_gen_v2_00_b
Connect ll_data_gen LLSRC to CDMAC_2_LLDST
Lock all other addresses in System Assembly view
Found PARAMETER C_CDMAC_2_MPMC2_TO_PI_CLK_RATIO = 1 ? change back to 2
Set ll_gen DCR base allow 64 bytes
PARAMETER C_DCR_BASEADDR = 0b0100000000
PARAMETER C_DCR_HIGHADDR = 0b0100001111
ERROR:MDT - IPNAME:ll_data_gen INSTANCE:ll_data_gen_0 -
E:\WORKSPACES\ML505_Johns_Tests\ml505_ddr2_xxp_150mhz_75mhz_uarlite_noplb_cdm
ac_llgen\pcores\ll_data_gen_v2_00_b\data\ll_data_gen_v2_1_0.mpd line 45 -
PORT CLK must be connected in MHS.
Connect ll_gen Clock and Reset
PORT CLK = CLK_75MHz
PORT RST = sys_rst_in
Builds OK
TestApp Memory runs OK
Need to understand clocking requirements of various modules
New Software App ''datagen_1tft_jac'' based on reference datagen_1tft
change DCR base addresses
XDM dow fails program is too big for 16 KB BRAM
Increase in System Assembly to 128 KB
Synthesis fails trying to use ~ 66 BRAMs only 60 BRAMs available
NB LLDataGen also uses some BRAMs
Not allowed to change BRAM size for program to eg 80 KB must be a factor of 2 for bus
Check platform address map ...
ERROR:MDT - INST:lmb_bram_if_cntlr_0 BASEADDR-HIGHADDR:0000000000-0x00013fff -
E:\WORKSPACES\ML505_Johns_Tests\ml505_ddr2_xxp_150mhz_75mhz_uarlite_noplb_cdm
ac_llgen\system.mhs line 267 - For the current memory size of 0x00014000,
memory size is not of size 2^N!
Put program back in MPMC2 mem at 0x1000'0100 (where ddr mem test goes?)
Place and Map ~ 10 MINS
Routing ~ 5 mins
Builds ok
WARNING:MDT - Peripheral ll_data_gen_0 is not connected to any of the processors
in the system. Check for the following reasons.
1. ll_data_gen_0 is not connected to any of the buses connected to a
processor.
2. ll_data_gen_0 does not have adresses set correctly.
3. ll_data_gen_0's address is not within any of the bridge windows connected
to a processor.
INFO:MDT - List of peripherals addressable from processor instance microblaze_0
:
- lmb_bram_if_cntlr_0
- lmb_bram_if_cntlr_1
- opb_v20_0
- opb_uartlite_0
- opb_mdm_0
- opb_intc_0
- mpmc2_ddr2_xxc_150mhz_x64_mt4htf3264h_53e_0
XMD% dow datagen_1tft_jac.elf
section, .vectors.reset: 0x00000000-0x00000007
section, .vectors.sw_exception: 0x00000008-0x0000000f
section, .vectors.interrupt: 0x00000010-0x00000017
section, .vectors.hw_exception: 0x00000020-0x00000027
section, .text: 0x10000100-0x10001637
section, .init: 0x10001638-0x10001663
section, .fini: 0x10001664-0x10001683
section, .ctors: 0x10001684-0x1000168b
section, .dtors: 0x1000168c-0x10001693
section, .rodata: 0x10001694-0x10001964
section, .data: 0x10001968-0x100019ab
section, .jcr: 0x100019ac-0x100019af
section, .bss: 0x10001a00-0x1001132f
Downloaded Program datagen_1tft_jac.elf
Setting PC with Program Start Address 0x00000000 (vectors reset)
datagen_1tft_jac doesn't run
no print out , debugger view freezes
Tried setting mem_test_jac program start addr 0x10000100
also doesn't run
also went back to design ml505_ddr2_xxp_150mhz_75mhz_uarlite_noplb
before change to MPMC2 core
mem_test_jac.elf doesn't run at 0x10000100
reduced size of datagen_1tft_jac_2 code to fit in PLB BRAM
only use 1 descriptor (instead of 960)
Program runs but don't see data values in buffers change in Memory view
Wrote values to FIRST_DATA_ADDRESS_RX = 0x1FE00000 but only read 0's ??
Tried ''ml505_ddr2_xxp_150mhz_75mhz_jc-1'' again
This was a hack of ml505_ddr2_xxp_150mhz_75mhz_rh-1
This uses OPB interface to DDR2
Therefore Microblaze caches are disabled. No XCL interface.
Changed to use UARTLITE. At first didn't work.
Changed UART param to use 75000000 clk but this didn't fix it.
Added UART Interrupt and OPB INTC. This appeared to fix design?
Now test_app_mem runs and seems to access DDR2.
but later notice sometimes reads 0 instead of correct value !
note PIM clk ratios are 1 for OPB and CDMAC
CDMAC addr only 64 MB
''ml505_ddr2_xxp_150mhz_75mhz_jc-1a''
Add LL Data Gen again
connect to CDMAC
memory test sometimes reads 0 instead of correct value !
see same problem with ml505_ddr2_xxp_150mhz_75mhz_jc-1
didn't run enough tests to see before
''** FIX **''
''change PI CLK RATIO for OPB and CDMAC to 2 ''
rebuild ok
memory test now always reading correct value ok
run data_gen_jac with start address in MPMC2 DDR2 0x10000100
#define FIRST_DATA_ADDRESS_RX 0x12E00000
rx data buffer
fill with default values ok
set up RX dma descriptors
start capture
myAddr = CDMAC_RX_CURR_DESC_PTR; * (volatile unsigned long *) myAddr = (Xuint32)RxDescriptors;
don't see new data in buffer
can't read dcr registers in data_gen or cdma
-- myAddr = DATAGEN_B2T1 0x42A08098 read :0xFFFFFFFF
-- myAddr = CDMAC_RX_CURR_DESC_PTR 0x42A0801C read :0xFFFFFFFF
Reading $FFFFFFFF implies Read Timeout from DCR according to OPB to DCR spec doc
should read -- (Xuint32)RxDescriptors :0x10001D00
can't access DCR from debugger
XMD% mrd 0x42a08000
Cannot Read from target
ERROR(1061): Debug Memory Access Check Failed
Section, 0x42a08000-0x42a08003 Not Accessible from Processor Debug Inter
face
Noticed DCR bus wasn't connected to data_gen ip
Connected and rebuilt
Still can only read $FFFFFFFF from DCR reg
Try connecting up OPB DCR to OPB clk and reset, see spec doc
PORT OPB_dcrClk = CLK_75MHz
(but not PORT OPB_dcrRst = sys_rst_s as this gives an error )
Still can only read $FFFFFFFF from DCR reg
Remove OPB_dcrClk and dcrRst connections
Try changing OPB DCR base to 0xD0000000
and removing connection to CDMAC
leaving only OPB DCR to data_gen
Still can only read $FFFFFFFF from DCR reg
Removed connection to CDMAC DCR leaving only slave ll_gen DCR
Still can only read $FFFFFFFF from DCR reg
Tried following in OPB_DCR in mhs
PARAMETER C_OPB_AWIDTH = 32
PARAMETER C_OPB_DWIDTH = 32
PARAMETER C_FAMILY = virtex5
PORT OPB_Clk = CLK_75MHz
Still can only read $FFFFFFFF from DCR reg
''** FIX **''
''Changed ll_gen IP core ''
ll_data_gen to ''ll_data_gen_v2_00_b'' v2.00b (was 2.00a)
Can now read DCR values !!
-- myAddr = DATAGEN_B2T1 0xD0000018 read :0xF5D74
(NB still can't access DCR memory from XMD ?)
RUNNING> XMD% mrd 0xd0000000 4
Cannot perform the Debug Command, Current Processor State is "Running"
ERROR(0):
XMD% stop
XMD% Info:User Interrupt, Processor Stopped at 0x100002a4
XMD% mrd 0xd0000000 4
Cannot Read from target
ERROR(1061): Debug Memory Access Check Failed
Section, 0xd0000000-0xd000000f Not Accessible from Processor Debug Inter
face
1)
4 x ML505 @ £612.83 x 4 = £2,451.32 + (vat £428.98)
= £2,880.30 + shipping
on 02/02/07 via email ; paid by GPC
2)
2 x ML555 @ £1111.11 x 2
4 x SMA-SATA @ 100.51 x 4 = 402.04
= 2,624.26 + (vat £459.24)
= £3,083.50 + shipping
paid by GPC
GPC charge = £ 3098.19 on 05/31/2007
(went on to FK50800 and was JV'd back to QQ10300)
BSB to create design
Error with clock IOB non optimal placing
Message To change to Warning Set user variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING 1
V4FX12
Power on Terminal settings with DCE jumpers
19200
8 bit
no parity
need to reset terminal?
Installing Quixtream under Linux on Dell 8250 te7kiribati
errors linking? example application
[esdg1@te7kiribati Installation-Files]$ ls
Qxtrm-Eth-UDP-1.12-1.i386.rpm WD900LNX86_64.tgz WD901LN.tgz
rpm -i
installs files to /opt/Quixilica
[esdg1@te7kiribati Qxtrm_UDPExample]$
[esdg1@te7kiribati Qxtrm_UDPExample]$ ls /opt/Quixilica/
doc examples netlists software vhdl
[esdg1@te7kiribati Qxtrm_UDPExample]$
then copy to home directory
[esdg1@te7kiribati Qxtrm_UDPExample]$ pwd
/home/esdg1/Quixilica/examples/C++/Qxtrm_UDPExample
[esdg1@te7kiribati Qxtrm_UDPExample]$ make clean
############################
# Cleaning out object files.
############################
[esdg1@te7kiribati Qxtrm_UDPExample]$ make
g++ -O3 -finline-functions -funroll-loops -fstrength-reduce -c -o QxtrmUDPExample.o QxtrmUDPExample.cpp
In file included from /usr/lib/gcc/i386-redhat-linux/3.4.4/../../../../include/c++/3.4.4/backward/iostream.h:31,
from QxtrmUDPExample.cpp:15:
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../../include/c++/3.4.4/backward/backward_warning.h:32:2: warning: #warning This file includes at least one deprecated or antiquated header. Please consider using one of the 32 headers found in section 17.4.1.2 of the C++ standard. Examples include substituting the <X> header for the <X.h> header for C++ includes, or <iostream> instead of the deprecated header <iostream.h>. To disable this warning use -Wno-deprecated.
############################
# Building program QxtrmUDPExample
############################
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x230): In function `Quixtream::Quixtream(char*, char*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x38a): In function `Quixtream::Quixtream(char*, char*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x4b5): In function `Quixtream::Quixtream(char*, char*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x566): In function `Quixtream::Quixtream(char*, char*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x671): In function `Quixtream::Quixtream(char*, char*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x748): more undefined references to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)' follow
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x218e): In function `Quixtream::ConstructChannels()':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x21a4): In function `Quixtream::ConstructChannels()':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x23c2): In function `Quixtream::ConstructChannels()':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x23e5): In function `Quixtream::ConstructChannels()':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x2408): In function `Quixtream::ConstructChannels()':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x24d9): In function `Quixtream::ConstructChannels()':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x24ec): In function `Quixtream::ConstructChannels()':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x26e9): In function `Quixtream::ConstructChannels()':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x270f): In function `Quixtream::ConstructChannels()':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x2735): In function `Quixtream::ConstructChannels()':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x287a): In function `Quixtream::ConstructChannels()':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x29ac): In function `Quixtream::ConstructChannels()':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.text+0x2a53): more undefined references to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)' follow
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.gnu.linkonce.t._ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag+0x25): In function `char* std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_construct<char const*>(char const*, char const*, std::allocator<char> const&, std::forward_iterator_tag)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_Rep::_S_create(unsigned int, std::allocator<char> const&)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.gnu.linkonce.t._ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag+0x69): In function `char* std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_construct<char const*>(char const*, char const*, std::allocator<char> const&, std::forward_iterator_tag)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrm.o)(.gnu.linkonce.t._ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag+0x76): In function `char* std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_construct<char const*>(char const*, char const*, std::allocator<char> const&, std::forward_iterator_tag)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmChannel.o)(.text+0x1cc): In function `QuixtreamChannel::QuixtreamChannel(qxtrmConfigChanType, qxtrmConfigChanDir, qxtrmConfigChanACK, unsigned int, qxtrmSocketUDPEthernetConfig*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmChannel.o)(.text+0x23d): In function `QuixtreamChannel::QuixtreamChannel(qxtrmConfigChanType, qxtrmConfigChanDir, qxtrmConfigChanACK, unsigned int, qxtrmSocketUDPEthernetConfig*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmChannel.o)(.text+0x4fc): In function `QuixtreamChannel::QuixtreamChannel(qxtrmConfigChanType, qxtrmConfigChanDir, qxtrmConfigChanACK, unsigned int, qxtrmSocketUDPEthernetConfig*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmChannel.o)(.text+0x56d): In function `QuixtreamChannel::QuixtreamChannel(qxtrmConfigChanType, qxtrmConfigChanDir, qxtrmConfigChanACK, unsigned int, qxtrmSocketUDPEthernetConfig*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmChannel.o)(.text+0xa14): In function `QuixtreamChannel::ConstructClass()':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmChannel.o)(.text+0xb3e): more undefined references to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)' follow
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmExceptions.o)(.text+0x6c): In function `QuixtreamGeneralException::QuixtreamGeneralException(std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmExceptions.o)(.text+0x7f): In function `QuixtreamGeneralException::QuixtreamGeneralException(std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmExceptions.o)(.text+0x118): In function `QuixtreamGeneralException::QuixtreamGeneralException(std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmExceptions.o)(.text+0x177): In function `QuixtreamGeneralException::QuixtreamGeneralException(std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmExceptions.o)(.text+0x218): In function `QuixtreamGeneralException::QuixtreamGeneralException(std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmExceptions.o)(.text+0x22b): In function `QuixtreamGeneralException::QuixtreamGeneralException(std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmExceptions.o)(.text+0x2c4): In function `QuixtreamGeneralException::QuixtreamGeneralException(std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmExceptions.o)(.text+0x323): In function `QuixtreamGeneralException::QuixtreamGeneralException(std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmExceptions.o)(.text+0x464): In function `QuixtreamParserException::QuixtreamParserException(qxtrmParserExceptionTag, std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, unsigned int)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmExceptions.o)(.text+0x4b3): In function `QuixtreamParserException::QuixtreamParserException(qxtrmParserExceptionTag, std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, unsigned int)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmExceptions.o)(.text+0x5ac): In function `QuixtreamParserException::QuixtreamParserException(qxtrmParserExceptionTag, std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, unsigned int)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmExceptions.o)(.text+0x5fb): more undefined references to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)' follow
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x1d55): In function `QuixtreamSystemConfig::GetNodeInSystemConfig(QuixtreamConfigID&)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x1d68): In function `QuixtreamSystemConfig::GetNodeInSystemConfig(QuixtreamConfigID&)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x1f65): In function `QuixtreamSystemConfig::GetNodeInSystemConfig(QuixtreamConfigID&)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x1f88): In function `QuixtreamSystemConfig::GetNodeInSystemConfig(QuixtreamConfigID&)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x1fab): In function `QuixtreamSystemConfig::GetNodeInSystemConfig(QuixtreamConfigID&)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x2055): In function `QuixtreamSystemConfig::GetNodeInSystemConfig(QuixtreamConfigID&)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x20c2): In function `QuixtreamSystemConfig::GetNodeInSystemConfig(QuixtreamConfigID&)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x212b): more undefined references to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)' follow
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x2336): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x2349): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x26df): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x2705): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x272b): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x2751): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x2777): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x279d): more undefined references to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)' follow
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x2837): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x284a): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x2a3e): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x2a61): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x2a84): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x2b19): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x2b86): In function `QuixtreamSystemConfig::GetProcessInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x2bf1): more undefined references to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)' follow
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x334e): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x3361): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x36f7): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x371d): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x3743): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x3769): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x378f): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x37b5): more undefined references to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)' follow
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x384f): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x3862): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x3a56): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x3a79): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x3a9c): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x3b31): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x3b9e): In function `QuixtreamSystemConfig::GetChannelInProcessConfig(QuixtreamConfigID&, qxtrmConfigProcess*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x3c09): more undefined references to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)' follow
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x4366): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x4379): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x470f): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x4735): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x475b): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x4781): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x47a7): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x47cd): more undefined references to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)' follow
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x4867): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x487a): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::basic_string<char, std::char_traits<char>, std::allocator<char> >::_S_empty_rep_storage'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x4a6e): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x4a91): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x4ab4): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x4b49): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x4bb6): In function `QuixtreamSystemConfig::GetInterfaceInNodeConfig(QuixtreamConfigID&, qxtrmConfigNode*)':
: undefined reference to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)'
/usr/lib/gcc/i386-redhat-linux/3.4.4/../../../libquixtream.a(qxtrmSystemConfig.o)(.text+0x4c21): more undefined references to `std::__default_alloc_template<true, 0>::deallocate(void*, unsigned int)' follow
collect2: ld returned 1 exit status
make: *** [QxtrmUDPExample] Error 1
[esdg1@te7kiribati Qxtrm_UDPExample]$ ls
Makefile QxtrmUDPExample.cpp QxtrmUDPExample.dsp QxtrmUDPExample.dsw QxtrmUDPExample.o QxtrmUDPExample.xml
[esdg1@te7kiribati Qxtrm_UDPExample]$
Quixtream Linux
From Quixtream User Manual
Linux tested with
Redhat Linux Fedora Core 6
(kernel 2.6.x and above)
GNU gcc 4.x and above
[esdg1@te7kiribati qxtrmUDP_v1_14_loopbackExample]$ pwd
/home/esdg1/Quixilica/examples/c++/qxtrmUDP_v1_14_loopbackExample
[esdg1@te7kiribati qxtrmUDP_v1_14_loopbackExample]$ ls
Makefile.linux Makefile.vxWorks QxtrmUDP_loopbackExample.cpp QxtrmUDP_loopbackExample.sln QxtrmUDP_loopbackExample.vcproj QxtrmUDP_loopbackExample.xml
[esdg1@te7kiribati qxtrmUDP_v1_14_loopbackExample]$ make -f Makefile.linux -n
g++ -O3 -m32 -finline-functions -funroll-loops -fstrength-reduce -c -o QxtrmUDP_loopbackExample.o QxtrmUDP_loopbackExample.cpp
echo ""
echo "############################"
echo "# Building program QxtrmUDP_loopbackExample"
echo "############################"
g++ -m32 -o QxtrmUDP_loopbackExample QxtrmUDP_loopbackExample.o -lquixtream -lpthread -lrt
[esdg1@te7kiribati qxtrmUDP_v1_14_loopbackExample]$ make -f Makefile.linux
g++ -O3 -m32 -finline-functions -funroll-loops -fstrength-reduce -c -o QxtrmUDP_loopbackExample.o QxtrmUDP_loopbackExample.cpp
############################
# Building program QxtrmUDP_loopbackExample
############################
[esdg1@te7kiribati qxtrmUDP_v1_14_loopbackExample]$ ls
Makefile.linux QxtrmUDP_loopbackExample QxtrmUDP_loopbackExample.o QxtrmUDP_loopbackExample.vcproj
Makefile.vxWorks QxtrmUDP_loopbackExample.cpp QxtrmUDP_loopbackExample.sln QxtrmUDP_loopbackExample.xml
Seems to have worked.
Like watching a Gorilla trying to play the harp.
ML403
http://www.xilinx.com/products/boards/ml403/reference_designs.htm
SL Meetings Actions
Delegation
Clear Description of Responsibilities
Do we need/want to recruit?
Spare key with HR
Avnet FAE . IP MPMC2 training? consultancy (support higher level options?)
''AGATA-DS''
Rob has 2 designs
1. ML505 design , compiles Saeed has copy
2. LocalLink generator ? consider putting on spare port
ISE 9.1 use get source from EDK (better integrated)
and copy EDK stub files (choose vhdl)
and ucf file
Update source code menu option (no more bmm files in Impact)
Saeed can insert in HDL designer
low level design are black boxes (rather than verilog files)
Rob hasn't tried OPB to DCR for microblaze
Inform Renato
Risk assessments
check being applied first
to SHE Dbase if Steve requests
let Miriam deal with Michelle
Quixtream 1.14 Tim using 64 bit linux on T2K
Hi John
HYPERLINK "file://\\fudge\ESDGshr\SDG\Projects\agata-Digitiser-snapshot\design" \\fudge\ESDGshr\SDG\Projects\agata-Digitiser-snapshot\design
ml505_ddr2_xxp_150mhz_75mhz_rh-2
The design in this folder includes the local link data generator - it's not finished and needs some clean up (deletion) of the local link signals being brought out as I/O versus those from the data generator. It was modified from the one I gave to Saeed.
You will have to ask Saeed for the other version where the local link is brought out.
ml505_ddr2_xxp_150mhz_75mhz_rh-1
Regards, Rob
Design 1 Takes CDMAC signals out of EDK design ie to connect to Saeed's Local Link block
Design 2 Includes a LL Generator module
Nb Rob got Local Link TFT code from : MPMC2 Projects
''ml403_ddr_idpoc_100mhz''
• Target Platform: ML403,
• Target Memory: DDR @ 32-bits, clocked at 100 MHz
• This design has a single PPC405, the PPC405 is clocked at 300 MHz
• This design has one PLB port, one OPB port, and one CDMAC port, all clocked at 100MHz.
• The PLB has a PLB_TFT rev_c controller to test bus mastership (Burst 32)
• The OPB has all OPB peripherals.
• The CDMAC has a ''LL_TFT controller'' and 1 ''LL Data generator''
• To swap between PLB_TFT and LL_TFT, use the W and E buttons on the ML403.
Rob gave Saeed memory controller verilog interface
So he could set DCR registers by hardware.
Better to use microblaze and system_stub
I gave Saeed verilog code
for Local Link Generator and TFT Controller (local link receiver)
John Womersley Aug 1 2007
"Deciding what NOT to do"
STFC 2K staff £700 M budget
PPAN strategy cttee over PPGP..
21 LFC projects from STFC definition > £25 M capital + 50 other research council projects
Sapphire Linear xray RAL idea
Hartree Centre Computational Research idea?
Square Kilometre Array
Government LFCF 100 M / yr
+ XFEL £30 M allocated already by LFCF
maximise in kind contribution eg Pixel detector => can spend money in UK rather than give to central pot
Technology
£20 M per year (cf £100 M industry?)
Sensors + Instrumentation
Technology Strategy Board at Swindon
Propose Technology Centres at STFC
Q. Researchers at STFC Henry Hutchinson review in progress
Q. Map to STFC Corporate Strategy?
Here is a new Tiddler
Links
*AGATA-DS Technical Docs*
ML505 - available now 2 Off;
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-V5-ML505-UNI-G&iLanguageID=1
[http://localhost/Reference_Files/ Reference Files]
[file:///E|/NewText.txt textfile]
[[JUNGO]]
[img[AGATA-DS2|file:///E|/TestImage.jpg][file:///E|/TestImage.jpg]]
image shack
<a href="http://img178.imageshack.us/my.php?image=agatads2rm9.jpg" target="_blank"><img src="http://img178.imageshack.us/img178/3126/agatads2rm9.th.jpg" border="0"/></a>
[img[http://img378.imageshack.us/img378/9771/agatads2eg9.jpg]]
[img[http://img297.imageshack.us/img297/5561/monetbatherstr3.jpg]]
Local files
[img[file:TestImage.jpg]]
[img[file:Pictures/Monet Bathers.jpg]]
Some more text
[img[file:///E|/TestImage.jpg]]
!My Headline
|!Table header|!Column Two|!My Column|
|>| colspan |
| rowspan |left aligned|test|
|~| right aligned|
|~| more stuff|
|bgcolor(#DC1A1A):colored| centered |
||*lists<br>*within<br>*tables<br><br>and double-spaced too|
|caption|c
----
''Bold Text''
//Italic Text//
__Underlined Text__
--Strike Through Text--
~GettingStarted
~GettingFinished
StyleSheet
@@color(green):green colored@@
{{indent{My text
#my item
#my second item
*my bullet
*my second bullet
**my third bullet
!My Headline
|!Table header|!Column Two|!My Column|
|>| colspan |
| rowspan |left aligned|
|~| right aligned|
|bgcolor(#DC1A1A):colored| centered |
||*lists<br>*within<br>*tables<br><br>and double-spaced too|
|caption|c
''Upgrading TiddlyWiki versions''
See http://www.tiddlywiki.com/
''Formatting''
http://www.giffmex.org/twfortherestofus.html
'Server for External Access''
Can copy TiddlyWiki html to web server to permit remote access.
http://www.te.rl.ac.uk/esdg/cms-fed/MyTiddlyWiki_OnServer.html
NB Can't edit the file via server link (can't change server contents)
Run XMD with design ml505_ddr2_xxp_150mhz_75mhz_uarlite2
Working
Microblaze(1) : microblaze_0
Address Map for Processor microblaze_0
(0000000000-0x00003fff) lmb_bram_if_cntlr_0 lmb_v10_1
(0000000000-0x00003fff) lmb_bram_if_cntlr_1 lmb_v10_0
(0x10000000-0x1fffffff) mpmc2_0 opb_v20_0->opb2plb_bridge_0->plb_v34_0
(0x10000000-0x1fffffff) mpmc2_0 microblaze_0_IXCL
(0x10000000-0x1fffffff) mpmc2_0 microblaze_0_DXCL
(0x40600000-0x40601fff) opb_uartlite_0 opb_v20_0
(0x41400000-0x4140ffff) opb_mdm_0 opb_v20_0
(0xd1000fc0-0xd1000fdf) opb_intc_0 opb_v20_0
XMD% dis 0x0 32
0: B8000000 bri 0
4: 00000000 add r0 , r0 , r0
8: 00000000 add r0 , r0 , r0
C: 00000000 add r0 , r0 , r0
This is bootloop code just endless loop returning to address 0 in BRAM
XMD% dow mem_test_jac.elf
section, .vectors.reset: 0x00000000-0x00000007
section, .vectors.sw_exception: 0x00000008-0x0000000f
section, .vectors.interrupt: 0x00000010-0x00000017
section, .vectors.hw_exception: 0x00000020-0x00000027
section, .text: 0x10000100-0x10001233
section, .init: 0x10001234-0x1000125f
section, .fini: 0x10001260-0x1000127f
section, .ctors: 0x10001280-0x10001287
section, .dtors: 0x10001288-0x1000128f
section, .rodata: 0x10001290-0x100016b8
section, .data: 0x100016c0-0x100016fb
section, .jcr: 0x100016fc-0x100016ff
section, .bss: 0x10001700-0x10001f0f
Downloaded Program mem_test_jac.elf
Setting PC with Program Start Address 0x00000000
BRAM
XMD% dis 0x0 32
0: B0001000 imm 4096
4: B8080100 brai 256 jump to program start address 0x10000100 in DDR2
8: B0001000 imm 4096
C: B80803EC brai 1004 user vector 0x100003ec
10: B0001000 imm 4096
14: B80807D0 brai 2000 interrupt 0x100007d0
18: 00000000 add r0 , r0 , r0
1C: 00000000 add r0 , r0 , r0
20: B0001000 imm 4096
24: B8080410 brai 1040 hardware exception 0x10000410
28: 00000000 add r0 , r0 , r0
2C: 00000000 add r0 , r0 , r0
30: 00000000 add r0 , r0 , r0
DDR2 memory start address
XMD% dis 0x10000100 32
10000100: B0001000 imm 4096
10000104: 31A01790 addik r13, r0 , 6032
10000108: B0001000 imm 4096
1000010C: 30401750 addik r2 , r0 , 5968
10000110: B0001000 imm 4096
10000114: 30201F00 addik r1 , r0 , 7936
10000118: B9F400A0 brlid r15, 160
1000011C: 80000000 Or r0 , r0 , r0
10000120: 20210010 addi r1 , r1 , 16
10000124: B8000000 bri 0
10000128: B0001000 imm 4096
1000012C: E0601700 lbui r3 , r0 , 5888
10000130: 3021FFE4 addik r1 , r1 , -28
10000134: F9E10000 swi r15, r1 , 0
Interrupt address
XMD% dis 0x100007d0 32
100007D0: 3021FFB0 addik r1 , r1 , -80
100007D4: F9E10000 swi r15, r1 , 0
100007D8: F8610020 swi r3 , r1 , 32
100007DC: F8810024 swi r4 , r1 , 36
100007E0: F8A10028 swi r5 , r1 , 40
100007E4: F8C1002C swi r6 , r1 , 44
100007E8: F8E10030 swi r7 , r1 , 48
100007EC: F9010034 swi r8 , r1 , 52
100007F0: F9210038 swi r9 , r1 , 56
100007F4: F941003C swi r10, r1 , 60
100007F8: F9610040 swi r11, r1 , 64
100007FC: F9810044 swi r12, r1 , 68
10000800: FA210048 swi r17, r1 , 72
10000804: 95608001 mfs r11, rMSR
10000808: B0001000 imm 4096
1000080C: E8A016D8 lwi r5 , r0 , 5848
10000810: B0001000 imm 4096
10000814: E86016D4 lwi r3 , r0 , 5844
10000818: FA41004C swi r18, r1 , 76
1000081C: F961001C swi r11, r1 , 28
10000820: 99FC1800 brald r15, r3
Must enable ''microblaze_0_xmdstub'' in BRAM
(instead of microblaze_0_bootloop)
to enable downloading elf files to memory with XMD
''NB elf file contains start address for execution''
ie no address is needed when downloading elf file in XMD
eg ML505 Tutorial with
TestApp_Memory in BRAM
TestApp_Peripheral in SRAM
Microblaze(1) : microblaze_0
Address Map for Processor microblaze_0 ''set in mhs''
(0000000000-0x0000ffff) dlmb_cntlr dlmb
(0000000000-0x0000ffff) ilmb_cntlr ilmb
(0x40000000-0x4000ffff) DIP_Switches_8Bit mb_opb
(0x40020000-0x4002ffff) Push_Buttons_5Bit mb_opb
(0x40040000-0x4004ffff) LEDs_Positions mb_opb
(0x40060000-0x4006ffff) LEDs_8Bit mb_opb
(0x40400000-0x4040ffff) RS232_Uart_2 mb_opb
(0x40420000-0x4042ffff) RS232_Uart_1 mb_opb
(0x40800000-0x4080ffff) IIC_EEPROM mb_opb
(0x40c00000-0x40c0ffff) Ethernet_MAC mb_opb
(0x41200000-0x4120ffff) opb_intc_0 mb_opb
(0x41400000-0x4140ffff) debug_module mb_opb
(0x41800000-0x4180ffff) SysACE_CompactFlash mb_opb
(0x41c00000-0x41c0ffff) opb_timer_1 mb_opb
(0x48f00000-0x48ffffff) SRAM_256Kx32 mb_opb
(0x50000000-0x5fffffff) DDR2_SDRAM_32Mx32 mb_opb
XMD% dow TestApp_Memory/executable.elf
section, .vectors.reset: 0x00000000-0x00000003
section, .vectors.sw_exception: 0x00000008-0x0000000b
section, .vectors.interrupt: 0x00000010-0x00000013
section, .vectors.hw_exception: 0x00000020-0x00000023
section, .text: 0x00000050-0x000012f7
section, .init: 0x000012f8-0x0000131b
section, .fini: 0x0000131c-0x00001337
section, .rodata: 0x00001338-0x0000147f
section, .data: 0x00001480-0x000014d3
section, .ctors: 0x000014d4-0x000014db
section, .dtors: 0x000014dc-0x000014e3
section, .jcr: 0x000014e4-0x000014e7
section, .bss: 0x000014e8-0x000014f3
section, .heap: 0x000014f4-0x000024f7
section, .stack: 0x000024f8-0x000034f7
Downloaded Program TestApp_Memory/executable.elf
Setting PC with Program Start Address 0x00000000
XMD% run
Info:Processor started. Type "stop" to stop processor
RUNNING> XMD% dow TestApp_Peripheral/executable.elf
Cannot perform the Debug Command, Current Processor State is "Running"
ERROR(0):
XMD% stop
XMD% Info:User Interrupt, Processor Stopped at 0x00000068
XMD% dow TestApp_Peripheral/executable.elf
section, .vectors.reset: 0x00000000-0x00000007
section, .vectors.sw_exception: 0x00000008-0x0000000f
section, .vectors.interrupt: 0x00000010-0x00000017
section, .vectors.hw_exception: 0x00000020-0x00000027
section, .text: 0x48f00000-0x48f0bb0b
section, .init: 0x48f0bb0c-0x48f0bb37
section, .fini: 0x48f0bb38-0x48f0bb57
section, .rodata: 0x48f0bb58-0x48f0c618
section, .sdata2: 0x48f0c619-0x48f0c61b
section, .data: 0x48f0c61c-0x48f0c84f
section, .ctors: 0x48f0c850-0x48f0c857
section, .dtors: 0x48f0c858-0x48f0c85f
section, .jcr: 0x48f0c860-0x48f0c863
section, .bss: 0x48f0c864-0x48f0f24f
section, .heap: 0x48f0f250-0x48f11253
section, .stack: 0x48f11254-0x48f13253
Downloaded Program TestApp_Peripheral/executable.elf
Setting PC with Program Start Address 0x00000000
XMD% run
Info:Processor started. Type "stop" to stop processor
display 4 words from address 0
''mrd 0x0 4''
write to addr 0
"mwr 0 0x10000100"